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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id u45si3308539qtc.5.2017.01.27.03.09.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 27 Jan 2017 03:09:50 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44399 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX4Pc-00075A-96 for patch@linaro.org; Fri, 27 Jan 2017 06:09:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX40I-0007bG-VX for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:43:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cX40F-0004cb-TK for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:43:39 -0500 Received: from mail-wm0-x234.google.com ([2a00:1450:400c:c09::234]:35291) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cX40F-0004bO-Mr for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:43:35 -0500 Received: by mail-wm0-x234.google.com with SMTP id r126so111089993wmr.0 for ; Fri, 27 Jan 2017 02:43:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y7zYZvE7n9D0dBB1IqY7SsdefFQddJx3kVYUDcVdxF0=; b=S6N03AI+JTd1DENHGQ2QR6BJsOF4Qty26Tyi1wzj2oEret54ObOUEvKYmOvKeg+F0Z CvYKVnOw7kqLcFyjRxC9vzbrXVFruSpYO0ax9DX7rMPFFaygrq80KD6nYJ+oPn+vot5l xTnD944AWpHoMFhBcCWNXZy8uFnL5proRaWfU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y7zYZvE7n9D0dBB1IqY7SsdefFQddJx3kVYUDcVdxF0=; b=rETDEOP1bXVIg6kf2bR+GGDMOSAtb9+e2c4wh9oh6xdluNM4z9UuuiiEjO133ZuWL3 x0bpWDoEMKvMDCdacVEp0Djk/OAdD9OfzNUjXr3yiLQxImelc9axRsSPCJX/iIBp8J3s SRybbrh/9gFBcrIoR96pI2NLHL3O43C5BCuBW5R4pURucoQwiOYVkoHmqQgf8C8dwO2r Gpj6NtmY4S5MYt843WaNA100o6SM3SX3AWFdAqeRuD+MCaO16ugKImL51jhysM051XsI Hq7ik+5BQnt5kfLtpbJpo+ByH1ENR5KuBg2OeAfQWjMub3+g9BNSt/F4lYrzbEIw4NTA oEOA== X-Gm-Message-State: AIkVDXKvvQ7EC5AhrGe5xAAJ8nCVXWnFQluxNlCgFeisfGZXftmf2/s23mZQRfEoPfmgQhuH X-Received: by 10.28.169.135 with SMTP id s129mr2415433wme.24.1485513814607; Fri, 27 Jan 2017 02:43:34 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id e6sm7183648wrc.30.2017.01.27.02.43.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jan 2017 02:43:33 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 38BDC3E376F; Fri, 27 Jan 2017 10:35:07 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: Date: Fri, 27 Jan 2017 10:35:02 +0000 Message-Id: <20170127103505.18606-23-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170127103505.18606-1-alex.bennee@linaro.org> References: <20170127103505.18606-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::234 Subject: [Qemu-devel] [PATCH v8 22/25] target-arm/cpu.h: make ARM_CP defined consistent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:ARM" , =?utf-8?q?Alex_Benn=C3=A9e?= , "open list:All patches CC here" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a purely mechanical change to make the ARM_CP flags neatly align and use a consistent format so it is easier to see which bit each flag is. Signed-off-by: Alex Bennée --- target/arm/cpu.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 2.11.0 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 274ef17562..f56a96c675 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1398,20 +1398,20 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) * need to be surrounded by gen_io_start()/gen_io_end(). In particular, * registers which implement clocks or timers require this. */ -#define ARM_CP_SPECIAL 1 -#define ARM_CP_CONST 2 -#define ARM_CP_64BIT 4 -#define ARM_CP_SUPPRESS_TB_END 8 -#define ARM_CP_OVERRIDE 16 -#define ARM_CP_ALIAS 32 -#define ARM_CP_IO 64 -#define ARM_CP_NO_RAW 128 -#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) -#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_SPECIAL (1 << 0) +#define ARM_CP_CONST (1 << 1) +#define ARM_CP_64BIT (1 << 2) +#define ARM_CP_SUPPRESS_TB_END (1 << 3) +#define ARM_CP_OVERRIDE (1 << 4) +#define ARM_CP_ALIAS (1 << 5) +#define ARM_CP_IO (1 << 6) +#define ARM_CP_NO_RAW (1 << 7) +#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) +#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) +#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) +#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */