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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id l62si12139080qkf.159.2017.02.01.07.44.32 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 01 Feb 2017 07:44:32 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51658 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cYx5E-0000rE-4t for patch@linaro.org; Wed, 01 Feb 2017 10:44:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39198) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cYwda-00008y-UU for qemu-devel@nongnu.org; Wed, 01 Feb 2017 10:16:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cYwdX-000203-Se for qemu-devel@nongnu.org; Wed, 01 Feb 2017 10:15:58 -0500 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:38508) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cYwdX-0001zh-N9 for qemu-devel@nongnu.org; Wed, 01 Feb 2017 10:15:55 -0500 Received: by mail-wm0-x230.google.com with SMTP id r141so42920102wmg.1 for ; Wed, 01 Feb 2017 07:15:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LU0eTWz6JUk8s/9OXBEjhieJgPfvfPccHT80d9Wbc+w=; b=Vbo9B4WkVKDfmAoeKYJfyTAOlRfr9J8YSvKCI1ACh2w3iYWXZCOED6XqO0fH5j1pd1 NRQKq1bTem/MHbgXipb4pKg+1jHUP13WZR2tZFkHguMXVXQsVMSl+GqGHoguvkiSug8N gmKJZbodomf++glU05Fh39qUfR4aNChTjnGco= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LU0eTWz6JUk8s/9OXBEjhieJgPfvfPccHT80d9Wbc+w=; b=i3AEUAYDn8o/VyCymzd7sfn3jp/nuJt//rOH5CkEafYZsO0C56dW2wcg+Kn70RJsYN Ey3L0ProBc959ugRcZvDShLZUE2kmo0zunLWodLZyuyZT1IC7QCQ3bj+RF/OvFMIG1tX AQ6fjsoQ7OmF62eA5W5KDkeUVacEUpyn/IQS4f3KZveudPA4G7EWaAIcHfebdtQsEsM7 3kr6wgrK54YnqBtUgvyBusKGoEAvgEGUWrxJDhfOWhkE/W6XP4r1rMtaO5Kwnksl208V WMFS0jcxIc9Skq8bpTF9kh9s2rmNgmLhqGXiqqCtBUYLXX1XSi4/I/bKK+y8lq5r9VPM GkSw== X-Gm-Message-State: AIkVDXIO2OKBebA2Tkq7bEcKLrttEySdvTk9wXlKolLtqCRXDVmI+8LW+4BlsN1gIsuUoUHG X-Received: by 10.223.171.12 with SMTP id q12mr3062568wrc.74.1485962154450; Wed, 01 Feb 2017 07:15:54 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id y30sm34649784wrc.23.2017.02.01.07.15.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Feb 2017 07:15:53 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 184463E0F74; Wed, 1 Feb 2017 15:05:55 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com Date: Wed, 1 Feb 2017 15:05:50 +0000 Message-Id: <20170201150553.9381-23-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170201150553.9381-1-alex.bennee@linaro.org> References: <20170201150553.9381-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::230 Subject: [Qemu-devel] [PATCH v9 22/25] target-arm/cpu.h: make ARM_CP defined consistent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, jan.kiszka@siemens.com, mark.burton@greensocs.com, "open list:ARM" , serge.fdrv@gmail.com, pbonzini@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, rth@twiddle.net Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a purely mechanical change to make the ARM_CP flags neatly align and use a consistent format so it is easier to see which bit each flag is. Signed-off-by: Alex Bennée --- target/arm/cpu.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 2.11.0 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 39bff86daf..d61793ca06 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1452,20 +1452,20 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) * need to be surrounded by gen_io_start()/gen_io_end(). In particular, * registers which implement clocks or timers require this. */ -#define ARM_CP_SPECIAL 1 -#define ARM_CP_CONST 2 -#define ARM_CP_64BIT 4 -#define ARM_CP_SUPPRESS_TB_END 8 -#define ARM_CP_OVERRIDE 16 -#define ARM_CP_ALIAS 32 -#define ARM_CP_IO 64 -#define ARM_CP_NO_RAW 128 -#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) -#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_SPECIAL (1 << 0) +#define ARM_CP_CONST (1 << 1) +#define ARM_CP_64BIT (1 << 2) +#define ARM_CP_SUPPRESS_TB_END (1 << 3) +#define ARM_CP_OVERRIDE (1 << 4) +#define ARM_CP_ALIAS (1 << 5) +#define ARM_CP_IO (1 << 6) +#define ARM_CP_NO_RAW (1 << 7) +#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) +#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) +#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) +#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */