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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:57 -0700 Message-Id: <20170906160612.22769-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: [Qemu-devel] [PULL 17/32] target/arm: [tcg, a64] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002340430.22386.10889954302345646107.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) -- 2.13.5 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f5c678ef25..e8dc96c28a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11200,21 +11200,12 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) free_tmp_a64(s); } -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) +static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu, int max_insns) { - CPUARMState *env = cs->env_ptr; - ARMCPU *cpu = arm_env_get_cpu(env); DisasContext *dc = container_of(dcbase, DisasContext, base); - target_ulong next_page_start; - int max_insns; - - dc->base.tb = tb; - dc->base.pc_first = dc->base.tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cs->singlestep_enabled; + CPUARMState *env = cpu->env_ptr; + ARMCPU *arm_cpu = arm_env_get_cpu(env); dc->pc = dc->base.pc_first; dc->condjmp = 0; @@ -11240,7 +11231,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len = 0; dc->vec_stride = 0; - dc->cp_regs = cpu->cp_regs; + dc->cp_regs = arm_cpu->cp_regs; dc->features = env->features; /* Single step state. The code-generation logic here is: @@ -11265,6 +11256,24 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, init_tmp_a64_array(dc); + return max_insns; +} + +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) +{ + CPUARMState *env = cs->env_ptr; + DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong next_page_start; + int max_insns; + + dc->base.tb = tb; + dc->base.pc_first = dc->base.tb->pc; + dc->base.pc_next = dc->base.pc_first; + dc->base.is_jmp = DISAS_NEXT; + dc->base.num_insns = 0; + dc->base.singlestep_enabled = cs->singlestep_enabled; + next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; max_insns = dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { @@ -11273,6 +11282,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, if (max_insns > TCG_MAX_INSNS) { max_insns = TCG_MAX_INSNS; } + max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns); gen_tb_start(tb);