From patchwork Mon Dec 18 17:45:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 122294 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3163697qgn; Mon, 18 Dec 2017 10:19:42 -0800 (PST) X-Google-Smtp-Source: ACJfBov2K/pFrhJpSF5NLycRq2ofQ2DqAGJrPhOMaKz9IWbqmnvzlDDnPGcNSdzZAb4vJUBYBFSf X-Received: by 10.129.198.13 with SMTP id l13mr542061ywi.334.1513621182656; Mon, 18 Dec 2017 10:19:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513621182; cv=none; d=google.com; s=arc-20160816; b=elhrKeCMoBgS8+Vw6FOycaRdJKtlBAGd0/pupBbqCu/Yxg6UsbVlYkRe1PUwvwOY+a YkskO3ZV8oHjYDtETEE1w2mvdl3wZDGzJTA+chU49xcMjLFcErhVzAzilsGopH+hNNmu jxC9MujU5UYZVYAfrqWKpeIVJRm8fxdBEMKxZOfuCfyD6jKw6ci0TsqNgRxTG8Xi6g5N RpSj1fdZrF0uCEDX1N5X4hbzzUcRRRfmLBoW5hVzCnua3VFW2loPVoZ2jOlr5vee3+yu qiGe5YrQnjyFljkl2FxcdSAPHygghtfzC/6x4a/weRzSHh6qZFTAZ/I2cuofirGkGO3+ 6JCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=gQ2kkF9An4v3zz2RnIXaDTstLgGEHB4P1MCQCEXfaFM=; b=Czxu6PFC+L75qpbaZDbPji7GMrqeNputzVAiYCEjvCZMJJfJNVyeQ9QhI8iaRYuq6d zb6FzZQOUpa8UmBThUycNiyoRvVTSim3PrxXUNoK4WkDVL/YhubVTt05v5qtO9Zpb6TK D4LGfFe5wjVShUVxTTHCZVqfK8bSSZ1Y8ywhmZeAc7dntem7goRueSgAHHwEASE9mGhV r9Oy8qxTaD/lT0EMRPD4MEn1LTaqPULEurdXELyJ/f1PhOCp/cOlJ/Wd6DiVKyQajhQ2 U5CXIc2pC73JDBVkBFHoWo5gPNieNjSpyokixszTh4N4h3GZliZlNT2ZjNUZ55gY26Zp R+PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WYuwpBbx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 134si2610466ybn.288.2017.12.18.10.19.42 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 18 Dec 2017 10:19:42 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WYuwpBbx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36022 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eR00s-0007bp-3o for patch@linaro.org; Mon, 18 Dec 2017 13:19:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55475) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eQzUI-00081V-1C for qemu-devel@nongnu.org; Mon, 18 Dec 2017 12:46:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eQzUG-0001nn-LM for qemu-devel@nongnu.org; Mon, 18 Dec 2017 12:46:02 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:40516) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eQzUG-0001nA-F9 for qemu-devel@nongnu.org; Mon, 18 Dec 2017 12:46:00 -0500 Received: by mail-pg0-x241.google.com with SMTP id k15so9432616pgr.7 for ; Mon, 18 Dec 2017 09:46:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gQ2kkF9An4v3zz2RnIXaDTstLgGEHB4P1MCQCEXfaFM=; b=WYuwpBbxF9PgrWrWhb68ihzzbJKA+no5t1Q183MlePzFyH5atBgsxiJghFo3nANy8X 1ongYR6mkT0owXaJX5eCPvgfzgUK2K98A9VwqvgZsFXgHWCQirgIzSFSs1t/bHNTgDPU cGuwTvPStDCH6W+/Yz+gQxYedPqHRzFowgJNA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gQ2kkF9An4v3zz2RnIXaDTstLgGEHB4P1MCQCEXfaFM=; b=b1eIgdCdww9nSsPfXacvuLotYBxt6Ltl54Ag8jgvGlweqXh98MekUHpb4W93B/0GSV Ya3aIVzfmilHMCfHdBACSBprSsLSSVxoIu4U+T0cS/tnVKm//0yCjuJKHmk1ld5X92tL UGw58hyyyW/lLAtYwvTB4GGVMkyKzm42d93PNZLxhLxGs+pUkaGrzHhNZWCZd7Dw9Ipf t5opITrV2mU24xgYn3i+ey+uF7hC0Co1nMnCeqm0tpLWIONv9EDt5tVmVdUrM1wAbUnp SgSdIXax/V9nkb3hh0KGgh2GysO/QVs+epA26f0/zRyFELhitx6FDYgXK308wPRLr9q9 Oo7A== X-Gm-Message-State: AKGB3mKEi8nQ/zgyRIxIj7o54jUJ1ucyUZ3dlH9MsaQOXOTf3KFExjNM tarslFCH0xyc3MAozEF1yJR1pgVeYcg= X-Received: by 10.101.101.73 with SMTP id a9mr436893pgw.148.1513619159147; Mon, 18 Dec 2017 09:45:59 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-7-63.tukw.qwest.net. [174.21.7.63]) by smtp.gmail.com with ESMTPSA id t84sm26209657pfe.160.2017.12.18.09.45.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:45:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:45:32 -0800 Message-Id: <20171218174552.18871-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218174552.18871-1-richard.henderson@linaro.org> References: <20171218174552.18871-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH 03/23] target/arm: Implement SVE Bitwise Logical - Unpredicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These were the instructions that were stubbed out when introducing the decode skeleton. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 61 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 57 insertions(+), 4 deletions(-) -- 2.14.3 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 67ad94e310..43420fa124 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -32,6 +32,10 @@ #include "trace-tcg.h" #include "translate-a64.h" +typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); +typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, + uint32_t, uint32_t, uint32_t); + /* * Include the generated decoder. */ @@ -42,7 +46,56 @@ * Implement all of the translator functions referenced by the decoder. */ -void trans_AND_zzz(DisasContext *s, arg_AND_zzz *a, uint32_t insn) { unsupported_encoding(s, insn); } -void trans_ORR_zzz(DisasContext *s, arg_ORR_zzz *a, uint32_t insn) { unsupported_encoding(s, insn); } -void trans_EOR_zzz(DisasContext *s, arg_EOR_zzz *a, uint32_t insn) { unsupported_encoding(s, insn); } -void trans_BIC_zzz(DisasContext *s, arg_BIC_zzz *a, uint32_t insn) { unsupported_encoding(s, insn); } +static unsigned size_for_gvec(unsigned s) +{ + if (s <= 8) { + return 8; + } else { + return QEMU_ALIGN_UP(s, 16); + } +} + +static void do_genfn2(DisasContext *s, GVecGen2Fn *gvec_fn, + int esz, int rd, int rn) +{ + unsigned vsz = size_for_gvec(vec_full_reg_size(s)); + gvec_fn(esz, vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), vsz, vsz); +} + +static void do_genfn3(DisasContext *s, GVecGen3Fn *gvec_fn, + int esz, int rd, int rn, int rm) +{ + unsigned vsz = size_for_gvec(vec_full_reg_size(s)); + gvec_fn(esz, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), vsz, vsz); +} + +static void do_zzz_genfn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn) +{ + do_genfn3(s, gvec_fn, a->esz, a->rd, a->rn, a->rm); +} + +void trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_and); +} + +void trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + if (a->rn == a->rm) { /* MOV */ + do_genfn2(s, tcg_gen_gvec_mov, 0, a->rd, a->rn); + } else { + do_genfn3(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); + } +} + +void trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_xor); +} + +void trans_BIC_zzz(DisasContext *s, arg_BIC_zzz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_andc); +}