diff mbox series

[v10.5,18/20] target/arm: Use vector infrastructure for aa64 orr/bic immediate

Message ID 20180117161435.28981-19-richard.henderson@linaro.org
State New
Headers show
Series tcg: generic vector operations | expand

Commit Message

Richard Henderson Jan. 17, 2018, 4:14 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate-a64.c | 38 +++++++++++++++++---------------------
 1 file changed, 17 insertions(+), 21 deletions(-)

-- 
2.14.3

Comments

Peter Maydell Jan. 25, 2018, 5:24 p.m. UTC | #1 
On 17 January 2018 at 16:14, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/translate-a64.c | 38 +++++++++++++++++---------------------

>  1 file changed, 17 insertions(+), 21 deletions(-)


Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e8fc4bc27e..3b113f6b7c 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6135,7 +6135,6 @@  static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
     bool is_neg = extract32(insn, 29, 1);
     bool is_q = extract32(insn, 30, 1);
     uint64_t imm = 0;
-    int i;
 
     if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
         unallocated_encoding(s);
@@ -6221,28 +6220,25 @@  static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8,
                             vec_full_reg_size(s), imm);
     } else {
+        /* ORR or BIC, with BIC negation to AND handled above.  */
+        static const GVecGen2s ops[2] = {
+            { .fni8 = tcg_gen_or_i64,
+              .fniv = tcg_gen_or_vec,
+              .opc = INDEX_op_or_vec,
+              .vece = MO_64,
+              .prefer_i64 = TCG_TARGET_REG_BITS == 64 },
+            { .fni8 = tcg_gen_and_i64,
+              .fniv = tcg_gen_and_vec,
+              .opc = INDEX_op_and_vec,
+              .vece = MO_64,
+              .prefer_i64 = TCG_TARGET_REG_BITS == 64 }
+        };
         TCGv_i64 tcg_imm = tcg_const_i64(imm);
-        TCGv_i64 tcg_rd = new_tmp_a64(s);
-
-        for (i = 0; i < 2; i++) {
-            int foffs = vec_reg_offset(s, rd, i, MO_64);
-
-            if (i == 1 && !is_q) {
-                /* non-quad ops clear high half of vector */
-                tcg_gen_movi_i64(tcg_rd, 0);
-            } else {
-                tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);
-                if (is_neg) {
-                    /* AND (BIC) */
-                    tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);
-                } else {
-                    /* ORR */
-                    tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm);
-                }
-            }
-            tcg_gen_st_i64(tcg_rd, cpu_env, foffs);
-        }
 
+        tcg_gen_gvec_2s(vec_full_reg_offset(s, rd),
+                        vec_full_reg_offset(s, rd),
+                        is_q ? 16 : 8, vec_full_reg_size(s),
+                        tcg_imm, &ops[is_neg]);
         tcg_temp_free_i64(tcg_imm);
     }
 }