From patchwork Mon Jan 22 03:42:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125324 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp951177ljf; Sun, 21 Jan 2018 20:10:26 -0800 (PST) X-Google-Smtp-Source: AH8x225vh2pJMfgXjCH6yY6X55nF6IXpHvoQqJI88XW49y1w/+c8b+9pisNBRvG8w8wFsRtlg17Z X-Received: by 10.129.161.202 with SMTP id y193mr6466157ywg.228.1516594226795; Sun, 21 Jan 2018 20:10:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516594226; cv=none; d=google.com; s=arc-20160816; b=cJdZCrCHDz8wgz/DuGsyRn7gvhbGkW/yy5i2JtQt+xSdFITUJPSswIW5y7etowU8JR sXLFGJ++r9QKrrZCEPP1jhYv44UjZh7N2aBQ/hQI66mjGbQtYQfMWqLANlLgiaW3w913 /g6d8fIG69FX3jWsbmoHmNQtasneroFZW8K2LZN7CTfidzffAo1scYhaKijXZfQQzO3l NHVZSAnw857x96TqgdPW371h+9MQP5lPbvBkA2KnqXICcGWp3hqgySTAh31ytGvH19Vr ylM1pVeDwLIVCM+AJ9aWqLr7W0/sICLVssuldeogGUNRgyevwh83lphUsGGYFs7rQhLO uTsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=gCQ4YatksYou5Apg3tk5GECCViHRlF1RM7HQ34t2B0I=; b=pv0ChTmC86C5quGWyJiyCagj11zwXFF2+jWYg4oNCjL/ootvWtqae7GZoPS5tcbHL6 0+oOMy93R2CHOKq5IEvNzNZUdOB0vdNFTNtl03L8k/g6vef9n2bMLkye9dB2wYjtrp2I W84BX1QjdshDKPXU85P8jXMOrLCtGl//FHQzDuQPbo/kb7SBI0uk1tRpcxPuKMHaUdDX yT9ZA3A5iWsvHm3OXAd3Q2+P1JgLVDMFIiIN7CtuQ+meE1iE9wkaDN9+u93jGxaIyOoi Vs+XjUd2rJmTIpySBTdE3uQuOkN/jUweTkN0olEeMkR/x8uP+jsKdT2vMqzG7QjY1Ygo nLdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MjYCW8Nk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n10si3491186ywm.555.2018.01.21.20.10.26 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 21 Jan 2018 20:10:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MjYCW8Nk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41798 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edTRC-0000RC-4J for patch@linaro.org; Sun, 21 Jan 2018 23:10:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60406) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edT0k-0005ss-KY for qemu-devel@nongnu.org; Sun, 21 Jan 2018 22:43:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edT0j-0006gw-HW for qemu-devel@nongnu.org; Sun, 21 Jan 2018 22:43:06 -0500 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:42502) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1edT0j-0006gf-BA for qemu-devel@nongnu.org; Sun, 21 Jan 2018 22:43:05 -0500 Received: by mail-pf0-x241.google.com with SMTP id b25so6073875pfd.9 for ; Sun, 21 Jan 2018 19:43:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gCQ4YatksYou5Apg3tk5GECCViHRlF1RM7HQ34t2B0I=; b=MjYCW8NkY319mWBX5+b3WwpDViaTIR83LN0jpkhmjzbnNgG5jbH+f6ox2vovhAo/ZV +qQZvPk6ieLrniSBrHTqbQE0N2lEvPNvMd9eLMdI/H+NJyLdsSH59f6N2ykkYK0YEKS1 bNiUw9QS0DGmdbFzpkItktPpY8B9DhyE6dKtA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gCQ4YatksYou5Apg3tk5GECCViHRlF1RM7HQ34t2B0I=; b=KvEBPb2BWj9Skavz1diE4VqFs1wtjXsNNb0FH/Fc2yzBUiHaSukX7mb+mCR5kObIm3 28WbP9BbQKyZk0BdyY8TXR2AoS3mpl99oyGUzzhaFLo+TeP8WK1x9TEaom/MiISJ1MMh 2qjgnusRborqbpvidog+8gRb81oqbDvVdFk+qhr0VId7kZ58UkvK0Xeia+ROepmgoBOA aisc2Fc5Ae+ZBFRWTYwHW1mchnZNnJnMq8B/0ZArfnZBCkz6xAXVJJCrl1jEefnsQq/6 M16UjZUrfESqdGZBAlxbaPMjnGW/yyZ0e+Q572LNozE0tiXRhIlAIehSWv/i7chnCxqp dBjQ== X-Gm-Message-State: AKwxytdDPxg1sGTZD86zA1+GIFB5OrwHHpL9f4k5dNxtTwaO5wmaGZ6C 84OM8xqpQEkjlMFMBIZBDykdgdcffr4= X-Received: by 2002:a17:902:7448:: with SMTP id e8-v6mr2668204plt.420.1516592583968; Sun, 21 Jan 2018 19:43:03 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.43.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:43:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:42:05 -0800 Message-Id: <20180122034217.19593-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PULL 31/43] target/hppa: Implement B,GATE insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/mem_helper.c | 8 ++++++++ target/hppa/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8a87b8a9b3..79763b254c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -353,6 +353,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, extern const MemoryRegionOps hppa_io_eir_ops; extern const struct VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); +int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); #endif void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 9d93894019..e2f94faab5 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -123,6 +123,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, break; default: /* execute: promote to privilege level type & 3 */ prot = x_prot; + break; } /* ??? Check PSW_P and ent->access_prot. This can remove PROT_WRITE. */ @@ -318,4 +319,11 @@ target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr) } return phys; } + +/* Return the ar_type of the TLB at VADDR, or -1. */ +int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) +{ + hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr); + return ent ? ent->ar_type : -1; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e4a140b9a6..c064c9d17b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3771,6 +3771,53 @@ static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, return do_dbranch(ctx, iaoq_dest(ctx, disp), link, n); } +static DisasJumpType trans_b_gate(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned n = extract32(insn, 1, 1); + unsigned link = extract32(insn, 21, 5); + target_sreg disp = assemble_17(insn); + target_ureg dest = iaoq_dest(ctx, disp); + + /* Make sure the caller hasn't done something weird with the queue. + * ??? This is not quite the same as the PSW[B] bit, which would be + * expensive to track. Real hardware will trap for + * b gateway + * b gateway+4 (in delay slot of first branch) + * However, checking for a non-sequential instruction queue *will* + * diagnose the security hole + * b gateway + * b evil + * in which instructions at evil would run with increased privs. + */ + if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) { + return gen_illegal(ctx); + } + +#ifndef CONFIG_USER_ONLY + if (ctx->tb_flags & PSW_C) { + CPUHPPAState *env = ctx->cs->env_ptr; + int type = hppa_artype_for_page(env, ctx->base.pc_next); + /* If we could not find a TLB entry, then we need to generate an + ITLB miss exception so the kernel will provide it. + The resulting TLB fill operation will invalidate this TB and + we will re-translate, at which point we *will* be able to find + the TLB entry and determine if this is in fact a gateway page. */ + if (type < 0) { + return gen_excp(ctx, EXCP_ITLB_MISS); + } + /* No change for non-gateway pages or for priv decrease. */ + if (type >= 4 && type - 4 < ctx->privilege) { + dest = deposit32(dest, 0, 2, type - 4); + } + } else { + dest &= -4; /* priv = 0 */ + } +#endif + + return do_dbranch(ctx, dest, link, n); +} + static DisasJumpType trans_bl_long(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { @@ -3849,6 +3896,7 @@ static const DisasInsn table_branch[] = { { 0xe8004000u, 0xfc00fffdu, trans_blr }, { 0xe800c000u, 0xfc00fffdu, trans_bv }, { 0xe800d000u, 0xfc00dffcu, trans_bve }, + { 0xe8002000u, 0xfc00e000u, trans_b_gate }, }; static DisasJumpType trans_fop_wew_0c(DisasContext *ctx, uint32_t insn,