From patchwork Fri Feb 16 21:56:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 128648 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1015863ljc; Fri, 16 Feb 2018 13:56:43 -0800 (PST) X-Google-Smtp-Source: AH8x2240uc+NGhcaogq75wbDX6kliRLW3Kw10vwRkPcuQqAaLbfio4IEo/PsnwTXDmC9mD24Ja0v X-Received: by 10.37.172.162 with SMTP id x34mr5597507ybi.355.1518818203382; Fri, 16 Feb 2018 13:56:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518818203; cv=none; d=google.com; s=arc-20160816; b=zt011vnS+7/NL/FVqaL6neJjoZ3itn+Mv3pGAYaII19OyiuaBIvsG2fv6TpwOnWyW2 yXayN7qfCvvH7igOGLj6ma8DHrtdzfaL1EAur24OR2R848dHD/NlZLFWtHr82klEofhd G9G1kTaBQwKH0vy45Z2SZtyU6p0y6yna6ps9wGbX5TgHc7DBZSBZoDAMUQOyFqjqkxVq +vRqJWIoA5OiJq0LppkgmfRbEZ2olfKDQM/90zwgFcYCQ7QWdMFBS4EqTQpdQmzl4puk 9ohJKfopswsnEFcX8RMX78z1hjVFjGHoKYriyQ/wwtIBP5IEFbNbUXXZveS3Z9NXgk/v 59FA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Nr9Iyx5NP+Nh6KPd1lKtecWd674sH0+DBAayKxV8yEY=; b=I+MrzJFCv7MjC7sr3Tzss9d78/DMTsRrKgPWenOm+z6L40EYp+nJKfKIBHVT9tpLxy BAFwsAntWqcYKjjT3vPq+uRFtq9la7SBI9OOUb6707qKyWxNYRYahlfvUzwryefbLBfP udr/pCkiY2Msb4STal7fY5DvUNYKDVAkVvG5XVq8m10mnPidSSdi+vOhZxfXQUAyVumB FVF/iRS8chYdbEMZOVhJIz9Py98yzSITQkCrl3DvRTMrk/FE2Hj3aH7xPocTY4nmXu52 oBtfz80E2yH+m9dZoAiKzg23pu0YbqcJaGh6HyycilKdoOdZddmnLvMpliut7VuUwAEw 0Q3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gozcc76Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id e10si1262001ywh.130.2018.02.16.13.56.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 16 Feb 2018 13:56:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gozcc76Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36871 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emnzm-0006lg-Mk for patch@linaro.org; Fri, 16 Feb 2018 16:56:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40681) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emnzN-0006k9-90 for qemu-devel@nongnu.org; Fri, 16 Feb 2018 16:56:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emnzL-0007OV-Fy for qemu-devel@nongnu.org; Fri, 16 Feb 2018 16:56:17 -0500 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:44816) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1emnzL-0007OI-73 for qemu-devel@nongnu.org; Fri, 16 Feb 2018 16:56:15 -0500 Received: by mail-pl0-x241.google.com with SMTP id w21so2372380plp.11 for ; Fri, 16 Feb 2018 13:56:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Nr9Iyx5NP+Nh6KPd1lKtecWd674sH0+DBAayKxV8yEY=; b=gozcc76ZqeGHc6TTs4YjOEdnipzOs2AIW7ru4yGNmNX2UY11nlGsRgL6M2SU21e6SS qnRnxBsXmou8faiTfVU4aOjZeipSZDUPXJGpZ8FqJ2xngS4QB0GyO03a5kVEHJ4d0A9A Y0gYXLNyJgE+KvvZbHpucAqHUMvzsYWqqijw4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Nr9Iyx5NP+Nh6KPd1lKtecWd674sH0+DBAayKxV8yEY=; b=IzB40beXZy1lxKc9RJpEYtmhYFLQe1Wf+RKIQgj8AhWug6p9XD1jpQHz9P95viUnFt pvg6+aOY8woJ8aBJeq/h9qF+FXMDZRKH2sMi6SMlS4ICwlG4HNw6R3B+OtlB2oBYd8yt Cfwouis3OkrJb5j92PU3q4MbHIBrR34lj8QDijFlKcVlgY6tXCia70Xehv4c7ZjjAQx6 YgvLQvnFiqTgt0TD8S7PSGszZxODLJ7wazqFcPBAa9B6i/upV6sb5Yz3CxxCKu9ZaDqT L8WzcTsvY3CYKM2RhvJiIpjWQT+aB+eiMQMeskCVRoTn9GQVSp7v5A8QPMQuXUXWKQf/ VoNA== X-Gm-Message-State: APf1xPAcmTAuiVx7aA7KvfBYvx7kqTxBIAl888A7q2N4nCf2jAwej6s5 MJFk+2yEAIqNAFqKB8bpd4Vhl+laAI0= X-Received: by 2002:a17:902:f:: with SMTP id 15-v6mr6929574pla.419.1518818173758; Fri, 16 Feb 2018 13:56:13 -0800 (PST) Received: from cloudburst.twiddle.net ([50.0.192.64]) by smtp.gmail.com with ESMTPSA id b88sm39230538pfd.108.2018.02.16.13.56.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Feb 2018 13:56:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 16 Feb 2018 13:56:04 -0800 Message-Id: <20180216215608.13227-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180216215608.13227-1-richard.henderson@linaro.org> References: <20180216215608.13227-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH v3 1/5] linux-user: Implement aarch64 PR_SVE_SET/GET_VL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As an implementation choice, widening VL has zeroed the previously inaccessible portion of the sve registers. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 3 +++ target/arm/cpu.h | 1 + linux-user/syscall.c | 27 ++++++++++++++++++++++++ target/arm/cpu64.c | 41 +++++++++++++++++++++++++++++++++++++ 4 files changed, 72 insertions(+) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h index 604ab99b14..205265e619 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -19,4 +19,7 @@ struct target_pt_regs { #define TARGET_MLOCKALL_MCL_CURRENT 1 #define TARGET_MLOCKALL_MCL_FUTURE 2 +#define TARGET_PR_SVE_SET_VL 50 +#define TARGET_PR_SVE_GET_VL 51 + #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index de62df091c..f5fbb9b450 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -846,6 +846,7 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, #ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); #endif target_ulong do_arm_semihosting(CPUARMState *env); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 82b35a6bdf..cf00ce10f1 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10659,6 +10659,33 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; } #endif +#ifdef TARGET_AARCH64 + case TARGET_PR_SVE_SET_VL: + /* We cannot support either PR_SVE_SET_VL_ONEXEC + or PR_SVE_VL_INHERIT. Therefore, anything above + ARM_MAX_VQ results in EINVAL. */ + ret = -TARGET_EINVAL; + if (arm_feature(cpu_env, ARM_FEATURE_SVE) + && arg2 >= 0 && arg2 <= ARM_MAX_VQ * 16 && !(arg2 & 15)) { + CPUARMState *env = cpu_env; + int old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; + int vq = MAX(arg2 / 16, 1); + + if (vq < old_vq) { + aarch64_sve_narrow_vq(env, vq); + } + env->vfp.zcr_el[1] = vq - 1; + ret = vq * 16; + } + break; + case TARGET_PR_SVE_GET_VL: + ret = -TARGET_EINVAL; + if (arm_feature(cpu_env, ARM_FEATURE_SVE)) { + CPUARMState *env = cpu_env; + ret = ((env->vfp.zcr_el[1] & 0xf) + 1) * 16; + } + break; +#endif /* AARCH64 */ case PR_GET_SECCOMP: case PR_SET_SECCOMP: /* Disable seccomp to prevent the target disabling syscalls we diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1c330adc28..a0a81014b2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -363,3 +363,44 @@ static void aarch64_cpu_register_types(void) } type_init(aarch64_cpu_register_types) + +/* The manual says that when SVE is enabled and VQ is widened the + * implementation is allowed to zero the previously inaccessible + * portion of the registers. The corollary to that is that when + * SVE is enabled and VQ is narrowed we are also allowed to zero + * the now inaccessible portion of the registers. + * + * The intent of this is that no predicate bit beyond VQ is ever set. + * Which means that some operations on predicate registers themselves + * may operate on full uint64_t or even unrolled across the maximum + * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally + * may well be cheaper than conditionals to restrict the operation + * to the relevant portion of a uint16_t[16]. + * + * TODO: Need to call this for changes to the real system registers + * and EL state changes. + */ +void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) +{ + int i, j; + uint64_t pmask; + + assert(vq >= 1 && vq <= ARM_MAX_VQ); + + /* Zap the high bits of the zregs. */ + for (i = 0; i < 32; i++) { + memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); + } + + /* Zap the high bits of the pregs and ffr. */ + pmask = 0; + if (vq & 3) { + pmask = ~(-1ULL << (16 * (vq & 3))); + } + for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { + for (i = 0; i < 17; ++i) { + env->vfp.pregs[i].p[j] &= pmask; + } + pmask = 0; + } +}