[v2,04/14] target/arm: Clear SVE high bits for FMOV

Message ID	20180502221552.3873-5-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Wed, 2 May 2018 15:15:42 -0700 Message-Id: <20180502221552.3873-5-richard.henderson@linaro.org> In-Reply-To: <20180502221552.3873-1-richard.henderson@linaro.org> References: <20180502221552.3873-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v2 04/14] target/arm: Clear SVE high bits for FMOV Precedence: list Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Fixups for ARM_FEATURE_V8_FP16 \| expand [v2,00/14] target/arm: Fixups for ARM_FEATURE_V8_FP16 [v2,01/14] target/arm: Implement vector shifted SCVF/UCVF for fp16 [v2,02/14] target/arm: Implement vector shifted FCVT for fp16 [v2,03/14] target/arm: Fix float16 to/from int16 [v2,04/14] target/arm: Clear SVE high bits for FMOV [v2,05/14] target/arm: Implement FMOV (general) for fp16 [v2,06/14] target/arm: Implement FCVT (scalar, integer) for fp16 [v2,07/14] target/arm: Implement FCVT (scalar, fixed-point) for fp16 [v2,08/14] target/arm: Introduce and use read_fp_hreg [v2,09/14] target/arm: Implement FP data-processing (2 source) for fp16 [v2,10/14] target/arm: Implement FP data-processing (3 source) for fp16 [v2,11/14] target/arm: Implement FCMP for fp16 [v2,12/14] target/arm: Implement FCSEL for fp16 [v2,13/14] target/arm: Implement FMOV (immediate) for fp16 [v2,14/14] target/arm: Fix sqrt_f16 exception raising

Message ID

20180502221552.3873-5-richard.henderson@linaro.org

State

Superseded

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Wed,  2 May 2018 15:15:42 -0700
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Subject: [Qemu-devel] [PATCH v2 04/14] target/arm: Clear SVE high bits for
	FMOV
Precedence: list
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-stable@nongnu.org
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Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

target/arm: Fixups for ARM_FEATURE_V8_FP16 | expand

Commit Message

Richard Henderson May 2, 2018, 10:15 p.m. UTC

Use write_fp_dreg and clear_vec_high to zero the bits
that need zeroing for these cases.

Cc: qemu-stable@nongnu.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate-a64.c | 17 +++++------------
 1 file changed, 5 insertions(+), 12 deletions(-)

-- 
2.14.3

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7021a31b89..c64c3ed99d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5444,31 +5444,24 @@  static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
 
     if (itof) {
         TCGv_i64 tcg_rn = cpu_reg(s, rn);
+        TCGv_i64 tmp;
 
         switch (type) {
         case 0:
-        {
             /* 32 bit */
-            TCGv_i64 tmp = tcg_temp_new_i64();
+            tmp = tcg_temp_new_i64();
             tcg_gen_ext32u_i64(tmp, tcg_rn);
-            tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64));
-            tcg_gen_movi_i64(tmp, 0);
-            tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
+            write_fp_dreg(s, rd, tmp);
             tcg_temp_free_i64(tmp);
             break;
-        }
         case 1:
-        {
             /* 64 bit */
-            TCGv_i64 tmp = tcg_const_i64(0);
-            tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64));
-            tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
-            tcg_temp_free_i64(tmp);
+            write_fp_dreg(s, rd, tcg_rn);
             break;
-        }
         case 2:
             /* 64 bit to top half. */
             tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
+            clear_vec_high(s, true, rd);
             break;
         }
     } else {

[v2,04/14] target/arm: Clear SVE high bits for FMOV

Commit Message

Patch