From patchwork Tue Jul 3 05:57:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140904 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp781484ljj; Mon, 2 Jul 2018 23:20:57 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfqHHtLJrh87lMDjrhalS0nspVVBQ309axwa11Bc4bkkCHhYwZDxaCy03A0A/1CGLqhoInY X-Received: by 2002:a0c:e90c:: with SMTP id a12-v6mr10030927qvo.224.1530598857041; Mon, 02 Jul 2018 23:20:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530598857; cv=none; d=google.com; s=arc-20160816; b=Lgs/xnBqFwRkwEfhU5Ma7/ql0qiTqP5W6xeaEhwwIe5QEoawcOMQdhC3DkB8WLb8WR xuWOZp8HNirtBS5eXlfYg57slu0tWzZS3W+Clu6L2ppq/yDGTRLUMkBrY3YLAVwubmmb 0xVYWrWpYxOYzUPiMHrP1PESefAGprV0rUH/rPWfppe89u8PG0gZbmASZ3NL93lH2qGV QzHlvQuP40lYT0HGpCV8relFUoJhVHD+uSfcLoUf1p97v8HTulXUqYzGZDRgzOsAxB92 3jxB/fp7f2+rRCNc0T4Yyz+LESWizSf7EqHaChTimhxmMMnocW2lmVnW/fa4//HQt8ty qqvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=hC7irEfuBbFnTc7Ze1ZCB3rc2cq83UlzhqZVICueJao=; b=rWvFmGaWwkSxHzTczXWUz/UkCSX9KMHMWkK0WMXvShC4a9zsRHNe0YXth2R6a1UAHE xTx+a2STt+M3kSqUG2Abh9HV/b9mwA+ShgaJMvILLDax3EXz3WaIvxCrH3+tE4qLSeKS ObyWNCaApk4w/BFbWvbs8Rk1jv1fCMbMY7EzOIO7EEHG6xgbYaCLqWtBp7tkpnugj2nY 9Db6ME4/o43YkGj6BB2+e7Ibs3IIQHLEYXq4mbAf25hYm0VUo+wlx0oNSL4sFyOmyhjg sfhWVEhi/s6MSpqJ1bGDdnZ7iRGutDxFF4RwfqLTVCMGM66OtQBzcVz0KmjjM24Mf/yZ aY8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=BUmh7uHz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o2-v6si377859qto.294.2018.07.02.23.20.56 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:20:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=BUmh7uHz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:38062 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEgK-0004Kt-9z for patch@linaro.org; Tue, 03 Jul 2018 02:20:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39827) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKW-0002rF-Gm for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKT-0006yv-T0 for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:24 -0400 Received: from ozlabs.org ([203.11.71.1]:52583) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKT-0006vi-3I; Tue, 03 Jul 2018 01:58:21 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYMB0MTbz9sBJ; Tue, 3 Jul 2018 15:58:12 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597494; bh=aVS2gFIN8wMUj6HW1raMgi+7caIQqex88I1ycTzdwzY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BUmh7uHzDW3ExlUbWYNSoaHvFNw3CvRy+i1T0NTNPRSt9OJkOG6LVjEw0Y0EbXdXo x0u94iUbGUe3GY52iiykUaukh+Npsy/D3iez78nClX+RW82eFfOXkUFZ7ePqRGLCVD GuIPNh7+FPOshqUlNWmnB9zjo0jvbOjmYuONSMoo= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:48 +1000 Message-Id: <20180703055804.13449-20-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 19/35] target/ppc: Split out gen_st_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Move the guts of ST_ATOMIC to a function. Use foo_tl for the operations instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an explicit call to gen_check_align. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 97 +++++++++++++++++++++--------------------- 1 file changed, 49 insertions(+), 48 deletions(-) -- 2.17.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 361b178db8..53ca8f0114 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3151,54 +3151,55 @@ static void gen_ldat(DisasContext *ctx) } #endif -#define ST_ATOMIC(name, memop, tp, op) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - int len = MEMOP_GET_SIZE(memop); \ - uint32_t gpr_FC = FC(ctx->opcode); \ - TCGv EA = tcg_temp_local_new(); \ - TCGv_##tp t0, t1; \ - \ - gen_addr_register(ctx, EA); \ - if (len > 1) { \ - gen_check_align(ctx, EA, len - 1); \ - } \ - t0 = tcg_temp_new_##tp(); \ - t1 = tcg_temp_new_##tp(); \ - tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ - \ - switch (gpr_FC) { \ - case 0: /* add and Store */ \ - tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 1: /* xor and Store */ \ - tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 2: /* Or and Store */ \ - tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 3: /* 'and' and Store */ \ - tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 4: /* Store max unsigned */ \ - case 5: /* Store max signed */ \ - case 6: /* Store min unsigned */ \ - case 7: /* Store min signed */ \ - case 24: /* Store twin */ \ - gen_invalid(ctx); \ - break; \ - default: \ - /* invoke data storage error handler */ \ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ - } \ - tcg_temp_free_##tp(t0); \ - tcg_temp_free_##tp(t1); \ - tcg_temp_free(EA); \ -} - -ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) -#if defined(TARGET_PPC64) -ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) +static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) +{ + uint32_t gpr_FC = FC(ctx->opcode); + TCGv EA = tcg_temp_new(); + TCGv src, discard; + + gen_addr_register(ctx, EA); + src = cpu_gpr[rD(ctx->opcode)]; + discard = tcg_temp_new(); + + memop |= MO_ALIGN; + switch (gpr_FC) { + case 0: /* add and Store */ + tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 1: /* xor and Store */ + tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Or and Store */ + tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 3: /* 'and' and Store */ + tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Store max unsigned */ + case 5: /* Store max signed */ + case 6: /* Store min unsigned */ + case 7: /* Store min signed */ + case 24: /* Store twin */ + gen_invalid(ctx); + break; + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + } + tcg_temp_free(discard); + tcg_temp_free(EA); +} + +static void gen_stwat(DisasContext *ctx) +{ + gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); +} + +#ifdef TARGET_PPC64 +static void gen_stdat(DisasContext *ctx) +{ + gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); +} #endif static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)