From patchwork Tue Oct 16 17:49:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 148996 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp5452713lji; Tue, 16 Oct 2018 11:38:04 -0700 (PDT) X-Google-Smtp-Source: ACcGV63vSuLVLL/okgiLBg2yp+t31cWj9a0SnpfYSZwXKyuJe7sB0qe3cwT/HGSrrMg9m9pP2VBw X-Received: by 2002:a37:9442:: with SMTP id w63-v6mr21611583qkd.304.1539715083985; Tue, 16 Oct 2018 11:38:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539715083; cv=none; d=google.com; s=arc-20160816; b=c3uGhdi3rzv9niJUnz3xatZblpew2d3Pa/HvrNnkheI36yx1+vfo72V/CTdPTj3SLP tZQAahBXUaXdo30yQTj0uM3IAomaAHO9optEWSBgHqhV/HUotqQZrVe7aeuQmimFX1z5 bOT91fc0UnmlwiyB8C2W2uxrycDn5QQ/Kth/cvbwmrODeWCSj9UGLJ3Iw+cTbabNxLf5 iT3SRVjSGxicLoZbA4MWNf6J7qonJmCiBtzZIDK9XuVyBxhX9QVy5CtNQyZM2PkJcwpF NUUSkd7/BV2hl8vfnxcEPYG3+ZzcQ4YqrqLH7G/Qu8LswEbXTtnVkNZuqAt1I6oydBUO +/JQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=o+dgHPD7vn5MSQoXXXAwqx0gYM5oyfE8kduesNuHmck=; b=QgcW8AMrry98gwbRCe9HAsoqvntpMqGyDWtzyAh9WhdpGtuyCuYIbmyRdjSP0LHWwK 6wQv5dyKLsvLfKlYHLoe+Ll+Xkdhcni3t+kwVbV1d6lcWawGD5101CUOlA4fVzHwjqtr Ylh1iIY8j+3dV27xJRzPHiG2ITqZaFiOT3voLtlEud6LS3rDxLSRX6i1K9BrSgcw5gX2 EbcMuC6YogbCVUj3TvYqyil61frXRgWneCkiPXjkOnogWnf1ezxxZNwbM70wamm/5/VZ 9Icqn2NMee8ugrbSNFKtBSFojbJzKKqoJIaCpuzs7Xxz5upheR9eWCxId5W8nY4IOxqH FxcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BAk+n0bx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f63-v6si2419170qkf.256.2018.10.16.11.38.03 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 16 Oct 2018 11:38:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BAk+n0bx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59686 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCUEF-0004uP-0B for patch@linaro.org; Tue, 16 Oct 2018 14:38:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59843) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTT-0004AK-2K for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTR-0001CF-H5 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:42 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:43449) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTR-0001BL-7o for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:41 -0400 Received: by mail-pl1-x630.google.com with SMTP id 30-v6so11351615plb.10 for ; Tue, 16 Oct 2018 10:49:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=o+dgHPD7vn5MSQoXXXAwqx0gYM5oyfE8kduesNuHmck=; b=BAk+n0bxV7mUWbCWVBDVswWQ7qRgYBiw06rC+bUtN6Cvla62sySozVQbi/nN7kt+50 8Gq6Vaxi/saKuLmwlTMhJw78xbe7Kq+sZmkegWCS1dO98olHBn6+PWnQPmvbG4gAT0Nx 26MnOV4zCH93kZKW2+lroKOpZPMFX8BoWYnSE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=o+dgHPD7vn5MSQoXXXAwqx0gYM5oyfE8kduesNuHmck=; b=AFp8L8AUKiDTchBtIESZdDttX+Cfj5ZVjcdhWvG30J6v49a1rJS0PUSWEf+zQzzTlZ bb9NmGqtMwzKeQV9K1oUSWOAYm4KKvLIxvty93ug5+6UVG3QfDEZYz0o+kV5eqiyTb6f +QBTSQeYCH9Ea13Nj1hCvKkI6q9mzgzZ/qupVysxfL3ShMelaoXJGyurYv8rHFlJPCwn wcVq/sJk1aRDs8PCknU7xLD6N7DnkDhr2huqu4or+pc0RqwIWqkAXDr3jzzrT9TlPi3o fNsITrXpPqkEUj2ftKafdAnTelbFmH/qwMYyGYcWEOmuaDEhFRzvN/a+uLhzGgYHZgbB LbGA== X-Gm-Message-State: ABuFfogEEpVzurJb+0njjGOZ2E43R0BX2n+ijJENEdI4xyXBybMqTj2+ TKEZoFMZhMXyLreIpORH/p8dzYtkY+w= X-Received: by 2002:a17:902:5a45:: with SMTP id f5-v6mr22705982plm.26.1539712179564; Tue, 16 Oct 2018 10:49:39 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:07 -0700 Message-Id: <20181016174911.9052-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::630 Subject: [Qemu-devel] [PULL 17/21] target/s390x: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/mem_helper.c | 92 +++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 51 deletions(-) -- 2.17.2 diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index bacae4f503..e106f61b4e 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" +#include "qemu/atomic128.h" #if !defined(CONFIG_USER_ONLY) #include "hw/s390x/storage-keys.h" @@ -1389,7 +1390,7 @@ static void do_cdsg(CPUS390XState *env, uint64_t addr, bool fail; if (parallel) { -#ifndef CONFIG_ATOMIC128 +#if !HAVE_CMPXCHG128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else int mem_idx = cpu_mmu_index(env, false); @@ -1435,9 +1436,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { -#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_ATOMIC128) uint32_t mem_idx = cpu_mmu_index(env, false); -#endif uintptr_t ra = GETPC(); uint32_t fc = extract32(env->regs[0], 0, 8); uint32_t sc = extract32(env->regs[0], 8, 8); @@ -1465,18 +1464,20 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, probe_write(env, a2, 0, mem_idx, ra); #endif - /* Note that the compare-and-swap is atomic, and the store is atomic, but - the complete operation is not. Therefore we do not need to assert serial - context in order to implement this. That said, restart early if we can't - support either operation that is supposed to be atomic. */ + /* + * Note that the compare-and-swap is atomic, and the store is atomic, + * but the complete operation is not. Therefore we do not need to + * assert serial context in order to implement this. That said, + * restart early if we can't support either operation that is supposed + * to be atomic. + */ if (parallel) { - int mask = 0; -#if !defined(CONFIG_ATOMIC64) - mask = -8; -#elif !defined(CONFIG_ATOMIC128) - mask = -16; + uint32_t max = 2; +#ifdef CONFIG_ATOMIC64 + max = 3; #endif - if (((4 << fc) | (1 << sc)) & mask) { + if ((HAVE_CMPXCHG128 ? 0 : fc + 2 > max) || + (HAVE_ATOMIC128 ? 0 : sc > max)) { cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } } @@ -1546,16 +1547,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, Int128 cv = int128_make128(env->regs[r3 + 1], env->regs[r3]); Int128 ov; - if (parallel) { -#ifdef CONFIG_ATOMIC128 - TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - ov = helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra); - cc = !int128_eq(ov, cv); -#else - /* Note that we asserted !parallel above. */ - g_assert_not_reached(); -#endif - } else { + if (!parallel) { uint64_t oh = cpu_ldq_data_ra(env, a1 + 0, ra); uint64_t ol = cpu_ldq_data_ra(env, a1 + 8, ra); @@ -1567,6 +1559,13 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra); cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); + } else if (HAVE_CMPXCHG128) { + TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + ov = helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra); + cc = !int128_eq(ov, cv); + } else { + /* Note that we asserted !parallel above. */ + g_assert_not_reached(); } env->regs[r3 + 0] = int128_gethi(ov); @@ -1596,18 +1595,16 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, cpu_stq_data_ra(env, a2, svh, ra); break; case 4: - if (parallel) { -#ifdef CONFIG_ATOMIC128 + if (!parallel) { + cpu_stq_data_ra(env, a2 + 0, svh, ra); + cpu_stq_data_ra(env, a2 + 8, svl, ra); + } else if (HAVE_ATOMIC128) { TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 sv = int128_make128(svl, svh); helper_atomic_sto_be_mmu(env, a2, sv, oi, ra); -#else + } else { /* Note that we asserted !parallel above. */ g_assert_not_reached(); -#endif - } else { - cpu_stq_data_ra(env, a2 + 0, svh, ra); - cpu_stq_data_ra(env, a2 + 8, svl, ra); } break; default: @@ -2105,21 +2102,18 @@ static uint64_t do_lpq(CPUS390XState *env, uint64_t addr, bool parallel) uintptr_t ra = GETPC(); uint64_t hi, lo; - if (parallel) { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else + if (!parallel) { + check_alignment(env, addr, 16, ra); + hi = cpu_ldq_data_ra(env, addr + 0, ra); + lo = cpu_ldq_data_ra(env, addr + 8, ra); + } else if (HAVE_ATOMIC128) { int mem_idx = cpu_mmu_index(env, false); TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 v = helper_atomic_ldo_be_mmu(env, addr, oi, ra); hi = int128_gethi(v); lo = int128_getlo(v); -#endif } else { - check_alignment(env, addr, 16, ra); - - hi = cpu_ldq_data_ra(env, addr + 0, ra); - lo = cpu_ldq_data_ra(env, addr + 8, ra); + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } env->retxl = lo; @@ -2142,21 +2136,17 @@ static void do_stpq(CPUS390XState *env, uint64_t addr, { uintptr_t ra = GETPC(); - if (parallel) { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx = cpu_mmu_index(env, false); - TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - - Int128 v = int128_make128(low, high); - helper_atomic_sto_be_mmu(env, addr, v, oi, ra); -#endif - } else { + if (!parallel) { check_alignment(env, addr, 16, ra); - cpu_stq_data_ra(env, addr + 0, high, ra); cpu_stq_data_ra(env, addr + 8, low, ra); + } else if (HAVE_ATOMIC128) { + int mem_idx = cpu_mmu_index(env, false); + TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + Int128 v = int128_make128(low, high); + helper_atomic_sto_be_mmu(env, addr, v, oi, ra); + } else { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } }