From patchwork Fri Dec 7 10:36:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 153119 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp341422ljp; Fri, 7 Dec 2018 02:45:37 -0800 (PST) X-Google-Smtp-Source: AFSGD/VvK2ixskjcEngpvykxeiZBv3BssYOpJAG68nF18zjRurCR85J0ywz6IizoRIUukwkGpRsz X-Received: by 2002:ac8:2eb8:: with SMTP id h53mr1427910qta.18.1544179537489; Fri, 07 Dec 2018 02:45:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544179537; cv=none; d=google.com; s=arc-20160816; b=pdBD+cn/zKb7zhyKJ0HNkNlnuUmBrEuNzImu6GAn58nqsK+rYl/0nNxbuXgQt6craq MtYahwjcnqsl4C0XdaHO6Fwh2/TJ40KZmqaoLZr46jnvVCgBAOXWm7ErhOKo7Qf7T9hB vqq85C7QYizkafiO7dY8JBeFnO38MjSBMkcNAXeKwhxZUHmh34ucPhHgulxC+ZvdalIU Y6x9G4d6kB5ZasR4q6qGwa0jAJzQh7A93w5kV0SZUbOplZhf0yvQSzlxpEWTHwVijrKr iYSt65GioZ7uGFQBYfMKPw+KvnlQroMi01TbAvfCprZ6vJ3EMvb6DM280lQFyhn3fP+z mqqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=wX3ccSw4O9RNkScWYoSfbfKoW98SciKAV8QH4pR1k8Q=; b=l6v55xTuPV4L+wjmzqBgYkTdp9lzfTQa9+NSHFBoykUpipAk3l1LTc+4N83WzVDgTh rJNw/WBi0+05OZ9TF/Y09yM+hXH2ahQkyscIAh+L9qVv4tzNBqGo3SRuA9wswDe/Wn+g JMB54Mw2AdLaXphnV/DQ742zgl8O6iFArOsjWPN85KnwDE61gUCD425RG+bzfirkXNIE Hj9oE+C7J8PjejbaIvpxa3bHJHVYMFcaj2LgaJ0qCEyoELaObl8y8Gf7fOFQZ6w47eL5 8+9R8uBJwJykyBQSJvc68K21dg/37d+0wYVCVTq39Wq3cK8vcMCWhqkLtFpltnDu7E2P vpuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Vebv5Rq3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p58si1707040qtb.253.2018.12.07.02.45.37 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 07 Dec 2018 02:45:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Vebv5Rq3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45294 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDdW-0002BZ-Kt for patch@linaro.org; Fri, 07 Dec 2018 05:45:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59246) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gVDVH-0008EA-4y for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gVDVG-0007sD-7A for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:03 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:33509) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gVDVG-0007qb-1T for qemu-devel@nongnu.org; Fri, 07 Dec 2018 05:37:02 -0500 Received: by mail-oi1-x241.google.com with SMTP id c206so3018048oib.0 for ; Fri, 07 Dec 2018 02:37:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wX3ccSw4O9RNkScWYoSfbfKoW98SciKAV8QH4pR1k8Q=; b=Vebv5Rq3Dzk+fSwWHmLbBlHmg2aJbaiuMZMwNCcrgpvCMFcBFxT4XdnONJnJR+3A7W z/nXIo+2NJx342Y3McEVqSrR7h6dn40+I7smPjUONXT7BghFzsAdU7T1GdtIuVyntTY9 zpQBDaUa4hCy1XOGS+Htw85XLR66minkgT1+E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wX3ccSw4O9RNkScWYoSfbfKoW98SciKAV8QH4pR1k8Q=; b=jYRydcytMy1I6hWChTfFxeQRKxfVpXdR0u5fSUnjFMDcHpHW26cCFJRjZEeymvhx32 OcpUgkKy08nDKNhwMLO5eRha3EURWeUFNIG9AxH578dT2MaeU168cBmQCkoYqRT/txV5 vGgInM2bVAfUtw6tvS5mSovkru2d2KY6y0Cpg8O0uPh/2nPSTHqjiyb0xfAzaAMhbqKE YOcpFC98EDYMaGYbTdxnE75OfdVPxi6Hy9ot+8UsCLSztn++e6AD/DSTztIM+TnROB9p gGZ5KYvqpX8fSjD8WfUXESAhJcK4ZhLAe4SDLDFm9jyCIDoWyGqoxt8G7DSqXUy4r6uI s8TQ== X-Gm-Message-State: AA+aEWZMcHFLFPpsnAHj4xAoJfYH6kciEJffhGwIpPlq05Ws2Y6mDROx RyvwjeIXXQa5OIljY4ThGGDZYqFdF/Q= X-Received: by 2002:aca:a60d:: with SMTP id p13mr979833oie.2.1544179021126; Fri, 07 Dec 2018 02:37:01 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm2037594otl.16.2018.12.07.02.36.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Dec 2018 02:37:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 7 Dec 2018 04:36:22 -0600 Message-Id: <20181207103631.28193-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181207103631.28193-1-richard.henderson@linaro.org> References: <20181207103631.28193-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH 17/26] target/arm: Reuse aa64_va_parameters for setting tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ramana.radhakrishnan@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 35 ----------------------------- target/arm/helper.c | 55 +++++++++------------------------------------ 2 files changed, 10 insertions(+), 80 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6bac5c18d0..f7a0eace68 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3065,41 +3065,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) } #endif -#ifndef CONFIG_USER_ONLY -/** - * arm_regime_tbi0: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI0 value from the appropriate TCR for the current EL - * - * Returns: the TBI0 value. - */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); - -/** - * arm_regime_tbi1: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI1 value from the appropriate TCR for the current EL - * - * Returns: the TBI1 value. - */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); -#else -/* We can't handle tagged addresses properly in user-only mode */ -static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} - -static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} -#endif - void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags); diff --git a/target/arm/helper.c b/target/arm/helper.c index 99ceed2cab..3ad5909b1e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8967,48 +8967,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) return mmu_idx; } -/* Returns TBI0 value for current regime el */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); - - tcr = regime_tcr(env, mmu_idx); - el = regime_el(env, mmu_idx); - - if (el > 1) { - return extract64(tcr->raw_tcr, 20, 1); - } else { - return extract64(tcr->raw_tcr, 37, 1); - } -} - -/* Returns TBI1 value for current regime el */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); - - tcr = regime_tcr(env, mmu_idx); - el = regime_el(env, mmu_idx); - - if (el > 1) { - return 0; - } else { - return extract64(tcr->raw_tcr, 38, 1); - } -} - /* Return the TTBR associated with this translation regime */ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) @@ -13041,9 +12999,16 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *pc = env->pc; flags = ARM_TBFLAG_AARCH64_STATE_MASK; - /* Get control bits for tagged addresses */ - flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); - flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); + +#ifndef CONFIG_USER_ONLY + /* Get control bits for tagged addresses. Note that the + * translator only uses this for instruction addresses. + */ + flags |= (aa64_va_parameters(env, 0, mmu_idx, false).tbi + << ARM_TBFLAG_TBI0_SHIFT); + flags |= (aa64_va_parameters(env, -1, mmu_idx, false).tbi + << ARM_TBFLAG_TBI1_SHIFT); +#endif if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el = sve_exception_el(env, current_el);