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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id D339E1FF92; Mon, 25 Mar 2019 13:20:09 +0000 (UTC) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Mon, 25 Mar 2019 13:20:05 +0000 Message-Id: <20190325132009.14987-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190325132009.14987-1-alex.bennee@linaro.org> References: <20190325132009.14987-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b Subject: [Qemu-devel] [PULL 5/9] target/mips: Fix minor bug in FPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org, Mateja Marjanovic Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Mateja Marjanovic Wrong type of NaN was generated for IEEE 754-2008 by MADDF. and MSUBF. instructions when the arguments were (Inf, Zero, NaN) or (Zero, Inf, NaN). The if-else statement establishes if the system conforms to IEEE 754-1985 or IEEE 754-2008, and defines different behaviors depending on that. In case of IEEE 754-2008, in mentioned cases of inputs, . returns the input value 'c' [2] (page 53) and raises floating point exception 'Invalid Operation' [1] (pages 349, 350). These scenarios were tested and the results in QEMU emulation match the results obtained on the machine that has a MIPS64R6 CPU. [1] MIPS Architecture for Programmers Volume II-a: The MIPS64 Instruction Set Reference Manual, Revision 6.06 [2] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module, Revision 1.12 Signed-off-by: Mateja Marjanovic Message-Id: <1553008916-15274-2-git-send-email-mateja.marjanovic@rt-rk.com> Reviewed-by: Peter Maydell [AJB: fixed up commit message] Signed-off-by: Alex Bennée -- 2.20.1 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 16c0bcb6fa..7b8895726c 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -495,15 +495,15 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_MIPS) - /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns - * the default NaN - */ - if (infzero) { - float_raise(float_flag_invalid, status); - return 3; - } - if (snan_bit_is_one(status)) { + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN + */ + if (infzero) { + float_raise(float_flag_invalid, status); + return 3; + } /* Prefer sNaN over qNaN, in the a, b, c order. */ if (is_snan(a_cls)) { return 0; @@ -519,6 +519,14 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 2; } } else { + /* + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + if (infzero) { + float_raise(float_flag_invalid, status); + return 2; + } /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2;