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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id d186sm19206675pfd.183.2019.05.18.12.14.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 18 May 2019 12:14:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 18 May 2019 12:14:30 -0700 Message-Id: <20190518191430.21686-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190518191430.21686-1-richard.henderson@linaro.org> References: <20190518191430.21686-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 2/2] target/ppc: Use tcg_gen_gvec_bitsel X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Replace the target-specific implementation of XXSEL. Signed-off-by: Richard Henderson --- target/ppc/translate/vsx-impl.inc.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 11d9b75d01..7a5d0e1f46 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1290,28 +1290,8 @@ static void glue(gen_, name)(DisasContext *ctx) \ VSX_XXMRG(xxmrghw, 1) VSX_XXMRG(xxmrglw, 0) -static void xxsel_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c) -{ - tcg_gen_and_i64(b, b, c); - tcg_gen_andc_i64(a, a, c); - tcg_gen_or_i64(t, a, b); -} - -static void xxsel_vec(unsigned vece, TCGv_vec t, TCGv_vec a, - TCGv_vec b, TCGv_vec c) -{ - tcg_gen_and_vec(vece, b, b, c); - tcg_gen_andc_vec(vece, a, a, c); - tcg_gen_or_vec(vece, t, a, b); -} - static void gen_xxsel(DisasContext *ctx) { - static const GVecGen4 g = { - .fni8 = xxsel_i64, - .fniv = xxsel_vec, - .vece = MO_64, - }; int rt = xT(ctx->opcode); int ra = xA(ctx->opcode); int rb = xB(ctx->opcode); @@ -1321,8 +1301,8 @@ static void gen_xxsel(DisasContext *ctx) gen_exception(ctx, POWERPC_EXCP_VSXU); return; } - tcg_gen_gvec_4(vsr_full_offset(rt), vsr_full_offset(ra), - vsr_full_offset(rb), vsr_full_offset(rc), 16, 16, &g); + tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(rt), vsr_full_offset(rc), + vsr_full_offset(rb), vsr_full_offset(ra), 16, 16); } static void gen_xxspltw(DisasContext *ctx)