| Message ID | 20190828190456.30315-57-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Convert aa32 base isa to decodetree | expand |
On 8/28/19 9:04 PM, Richard Henderson wrote: > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > target/arm/translate.c | 14 +------------- > target/arm/t16.decode | 10 ++++++++++ > 2 files changed, 11 insertions(+), 13 deletions(-) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index b7e2c72f35..d06ec48ab9 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -10743,21 +10743,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) > op = (insn >> 8) & 0xf; > switch (op) { > case 0: /* add/sub (sp, immediate), in decodetree */ > + case 2: /* sign/zero extend, in decodetree */ > goto illegal_op; > > - case 2: /* sign/zero extend. */ > - ARCH(6); > - rd = insn & 7; > - rm = (insn >> 3) & 7; > - tmp = load_reg(s, rm); > - switch ((insn >> 6) & 3) { > - case 0: gen_sxth(tmp); break; > - case 1: gen_sxtb(tmp); break; > - case 2: gen_uxth(tmp); break; > - case 3: gen_uxtb(tmp); break; > - } > - store_reg(s, rd, tmp); > - break; > case 4: case 5: case 0xc: case 0xd: > /* > * 0b1011_x10x_xxxx_xxxx > diff --git a/target/arm/t16.decode b/target/arm/t16.decode > index b425b86795..b5b5086e8a 100644 > --- a/target/arm/t16.decode > +++ b/target/arm/t16.decode > @@ -23,6 +23,7 @@ > &s_rrr_shr !extern s rn rd rm rs shty > &s_rri_rot !extern s rn rd imm rot > &s_rrrr !extern s rd rn rm ra > +&rrr_rot !extern rd rn rm rot > &ri !extern rd imm > &r !extern rm > &ldst_rr !extern p w u rn rt rm shimm shtype > @@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branchr > BLX_r 0100 0111 1 .... 000 @branchr > BXNS 0100 0111 0 .... 100 @branchr > BLXNS 0100 0111 1 .... 100 @branchr > + > +# Extend > + > +@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0 > + > +SXTAH 1011 0010 00 ... ... @extend > +SXTAB 1011 0010 01 ... ... @extend > +UXTAH 1011 0010 10 ... ... @extend > +UXTAB 1011 0010 11 ... ... @extend >
diff --git a/target/arm/translate.c b/target/arm/translate.c index b7e2c72f35..d06ec48ab9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10743,21 +10743,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) op = (insn >> 8) & 0xf; switch (op) { case 0: /* add/sub (sp, immediate), in decodetree */ + case 2: /* sign/zero extend, in decodetree */ goto illegal_op; - case 2: /* sign/zero extend. */ - ARCH(6); - rd = insn & 7; - rm = (insn >> 3) & 7; - tmp = load_reg(s, rm); - switch ((insn >> 6) & 3) { - case 0: gen_sxth(tmp); break; - case 1: gen_sxtb(tmp); break; - case 2: gen_uxth(tmp); break; - case 3: gen_uxtb(tmp); break; - } - store_reg(s, rd, tmp); - break; case 4: case 5: case 0xc: case 0xd: /* * 0b1011_x10x_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b425b86795..b5b5086e8a 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&rrr_rot !extern rd rn rm rot &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branchr BLX_r 0100 0111 1 .... 000 @branchr BXNS 0100 0111 0 .... 100 @branchr BLXNS 0100 0111 1 .... 100 @branchr + +# Extend + +@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0 + +SXTAH 1011 0010 00 ... ... @extend +SXTAB 1011 0010 01 ... ... @extend +UXTAH 1011 0010 10 ... ... @extend +UXTAB 1011 0010 11 ... ... @extend