diff mbox series

[16/78] target/arm: Set ISSIs16Bit in make_issinfo

Message ID 20200616141547.24664-17-mdroth@linux.vnet.ibm.com
State New
Headers show
Series Patch Round-up for stable 4.2.1, freeze on 2020-06-22 | expand

Commit Message

Michael Roth June 16, 2020, 2:14 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>


During the conversion to decodetree, the setting of
ISSIs16Bit got lost.  This causes the guest os to
incorrectly adjust trapping memory operations.

Cc: qemu-stable@nongnu.org
Fixes: 46beb58efbb8a2a32 ("target/arm: Convert T16, load (literal)")
Reported-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200117004618.2742-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

(cherry picked from commit 1a1fbc6cbb34c26d43d8360c66c1d21681af14a9)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>

---
 target/arm/translate.c | 3 +++
 1 file changed, 3 insertions(+)

-- 
2.17.1
diff mbox series

Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 83aa331b1e..ad052a2abd 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8556,6 +8556,9 @@  static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w)
     /* ISS not valid if writeback */
     if (p && !w) {
         ret = rd;
+        if (s->base.pc_next - s->pc_curr == 2) {
+            ret |= ISSIs16Bit;
+        }
     } else {
         ret = ISSInvalid;
     }