diff mbox series

[PULL,02/39] target/arm: Fix alignment for VLD4.32

Message ID 20220922163536.1096175-3-peter.maydell@linaro.org
State Accepted
Commit 3a661024cc680104ce2cd21f8f5466dacba6f405
Headers show
Series [PULL,01/39] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic | expand

Commit Message

Peter Maydell Sept. 22, 2022, 4:34 p.m. UTC 
From: Clément Chigot <chigot@adacore.com>

When requested, the alignment for VLD4.32 is 8 and not 16.

See ARM documentation about VLD4 encoding:
    ebytes = 1 << UInt(size);
    if size == '10' then
        alignment = if a == '0' then 1 else 8;
    else
        alignment = if a == '0' then 1 else 4*ebytes;

Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220914105058.2787404-1-chigot@adacore.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-neon.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index 321c17e2c7e..4016339d46f 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -584,7 +584,11 @@  static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
         case 3:
             return false;
         case 4:
-            align = pow2_align(size + 2);
+            if (size == 2) {
+                align = pow2_align(3);
+            } else {
+                align = pow2_align(size + 2);
+            }
             break;
         default:
             g_assert_not_reached();