From patchwork Sun Sep 25 10:51:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 609136 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1272039pvb; Sun, 25 Sep 2022 04:07:06 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5zJMSfQfFdG92e7AreMN+CbihQoIsVnW2VPtjfiFDtoAVsXsdPHbzPDsZ2H6QgLgs7rccb X-Received: by 2002:a0c:f4cc:0:b0:4aa:a471:978f with SMTP id o12-20020a0cf4cc000000b004aaa471978fmr13715322qvm.80.1664104026168; Sun, 25 Sep 2022 04:07:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664104026; cv=none; d=google.com; s=arc-20160816; b=jrJ/2B6xVX5HWndA0qPgi1c3KAL0RAuwTYqJRFwm76j1YGhkAJdoPG6VH02WHLJBo6 y9gQPt7+pbqY+jyYQVCbmeLvGH4pgZ0oneEx10vFik8OABjuNrDyKKcni82uw2LES1rV twGIcI0LQauwTvbMzqvWJYTznvYXfqdUUlJKlZq/4GPwAbezvOqtnJTqJKUnF8yOpMvX NK9RmM65ItguQy2DMzarKDsl7BDBxBWVBOfwePeWhI8+V3OAul/Al4mz+rvoucOISDXX Kb8+J4dn9eULJnd95UlS2qJ6NlURiD+/JHsGpnLCcZzSOoyQ+CLRnGHpzYvC2G9qTV3+ 8ZFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0AHQ15bdXv3V/XhfvkV/1ZzCa7qRaWxOYtuze5IOQL8=; b=wRdOWmaHeZBaTYoM2VbMCTVVKgRtaBKsEGaM1q8r57vyhz807QsJBLI/5tU9RAif2K xavwkDoaoG2O81XutRdzKqGujdGwrsjEMQhh9soT+zpkElOX7blzLhG+6iKryEz+2bbW WLapJk5Pd+B3bKSKjXaskrasqRhhy6saxPe7cInW+67j2R/J4Wwhzb1gYazMkMvlQ6I1 KaC46MceQVqSaHJPHZnvFkbIYKUhjLiocF5s0Lxmko2mXyVb3fKJTJs6I6L8GI0SVIOC MZdgEf/rnL5IhD57EltIEQpsGAJ2y2/zRwgCgB1IZXoC1TZLsQ5dO4BwJf3l/oNNLNwD c+0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b2SwHTV8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g14-20020ad457ae000000b004ad2cfb3b5bsi5496533qvx.7.2022.09.25.04.07.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 25 Sep 2022 04:07:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b2SwHTV8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39194 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocPTV-0007HA-M2 for patch@linaro.org; Sun, 25 Sep 2022 07:07:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocPEx-00032b-57 for qemu-devel@nongnu.org; Sun, 25 Sep 2022 06:52:03 -0400 Received: from mail-qk1-x72e.google.com ([2607:f8b0:4864:20::72e]:36535) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocPEv-0000NL-Jy for qemu-devel@nongnu.org; Sun, 25 Sep 2022 06:52:02 -0400 Received: by mail-qk1-x72e.google.com with SMTP id i3so2652391qkl.3 for ; Sun, 25 Sep 2022 03:52:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=0AHQ15bdXv3V/XhfvkV/1ZzCa7qRaWxOYtuze5IOQL8=; b=b2SwHTV8AGXreemtRS7m+vFY3ryBKri3ZOGIAc6eeWu7Gw1y2B35icbV7zKz4N6bQS 0+h8VbLRw6ewHopYviR5qxOGWPVZRkxjXOJaN0k0oyCdz5N5mF+pbAyU2IKOe8UyT/G8 z01WDEK700finS4jEMc69an7AZQyslscABias19a2VfhQdFWe+b+qTR7sKqI+1Pkogdt w1Xhski8DP59P/zNOmbXAdMk04eICRLA/ITQfFJJN/3yHBfeUmbbbxCDfYEMjAdqAcDn 2D+bh+LoO4P8YsX6sFYII63tBzo9Pcufe/f/WSLCR6WvvrZ6wTbyybGslmChXStZSKHl m5YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=0AHQ15bdXv3V/XhfvkV/1ZzCa7qRaWxOYtuze5IOQL8=; b=RaKHvvMu/BY7EGF8u1F32UE6PlsFu0gXHDN3pvJpjv6vQefYAS93Ot80YFuYJrXWdK h5HEjazWGrXlLSTZ2UDIyizhxeQUVTyYZXEYp1kg9tOcGBO8B6eUOX7KSMJOyRfprBj6 3CruUlHscwcH6bY+9yCiPs5Ps6RKW5ZUa/1qg+Wy0TlCAxwh7NBweo9de56W7ePy7tVV MzetkcynRiZS1oFrMMLIGoC+wmg3H+W/jcq+ATh75QPGlSR7mTz1u1u9Srlfkh0273l9 ImvpttG7cApylqJZdri2rT2lb78709c/4kLa1/wAxJKLIeDW+U0GhgOFW+il56iIxNK3 1E0Q== X-Gm-Message-State: ACrzQf1R/Ta/+7Zi0hIPO/J49LbOwYB6keoR/d/wJGRYC6hnc6pCoGlT s1RtnVNVBYIiV7UfUPIu3lQNbTsEULiZNw== X-Received: by 2002:ae9:ed8e:0:b0:6ce:7eb6:adb8 with SMTP id c136-20020ae9ed8e000000b006ce7eb6adb8mr11024359qkg.777.1664103120636; Sun, 25 Sep 2022 03:52:00 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a9:5c0e:1ec2:d482:4986:8538]) by smtp.gmail.com with ESMTPSA id u15-20020a05620a0c4f00b006cf19068261sm10061132qki.116.2022.09.25.03.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 03:52:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PATCH v5 09/17] accel/tcg: Add force_aligned to CPUTLBEntryFull Date: Sun, 25 Sep 2022 10:51:16 +0000 Message-Id: <20220925105124.82033-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220925105124.82033-1-richard.henderson@linaro.org> References: <20220925105124.82033-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Support per-page natural alignment checking. This will be used by Arm for pages mapped with memory type Device. Cc: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 3 +++ accel/tcg/cputlb.c | 20 +++++++++++++------- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 7c0ba93826..d0acbb4d35 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -167,6 +167,9 @@ typedef struct CPUTLBEntryFull { /* @byte_swap indicates that all accesses use inverted endianness. */ bool byte_swap; + /* @force_aligned indicates that all accesses must be aligned. */ + bool force_aligned; + /* * Allow target-specific additions to this structure. * This may be used to cache items from the guest cpu diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 1a5a6bd98b..01a89b4a1f 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1146,7 +1146,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, /* Repeat the MMU check and TLB fill on every access. */ address |= TLB_INVALID_MASK; } - if (full->byte_swap) { + if (full->byte_swap || full->force_aligned) { address |= TLB_SLOW_PATH; } @@ -1944,16 +1944,19 @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi, /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUTLBEntryFull *full; + CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; bool need_swap; /* For anything that is unaligned, recurse through full_load. */ if ((addr & (size - 1)) != 0) { + /* Honor per-page alignment requirements. */ + if (full->force_aligned) { + cpu_unaligned_access(env_cpu(env), addr, access_type, + mmu_idx, retaddr); + } goto do_unaligned_access; } - full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; - /* Handle watchpoints. */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { /* On watchpoint hit, this will longjmp out. */ @@ -2349,16 +2352,19 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUTLBEntryFull *full; + CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; bool need_swap; /* For anything that is unaligned, recurse through byte stores. */ if ((addr & (size - 1)) != 0) { + /* Honor per-page alignment requirements. */ + if (full->force_aligned) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, + mmu_idx, retaddr); + } goto do_unaligned_access; } - full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; - /* Handle watchpoints. */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { /* On watchpoint hit, this will longjmp out. */