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Tue, 18 Oct 2022 06:31:17 -0700 (PDT) X-Received: by 2002:aa7:d7c5:0:b0:459:fad8:fd2 with SMTP id e5-20020aa7d7c5000000b00459fad80fd2mr2670376eds.336.1666099877527; Tue, 18 Oct 2022 06:31:17 -0700 (PDT) Received: from avogadro.local ([2001:b07:6468:f312:2f4b:62da:3159:e077]) by smtp.gmail.com with ESMTPSA id l3-20020aa7cac3000000b0045723aa48ccsm8755833edt.93.2022.10.18.06.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 06:31:16 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PULL 09/53] target/i386: Use MMUAccessType across excp_helper.c Date: Tue, 18 Oct 2022 15:29:58 +0200 Message-Id: <20221018133042.856368-10-pbonzini@redhat.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221018133042.856368-1-pbonzini@redhat.com> References: <20221018133042.856368-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.256, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Replace int is_write1 and magic numbers with the proper MMUAccessType access_type and enumerators. Signed-off-by: Richard Henderson Message-Id: <20221002172956.265735-2-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini --- target/i386/tcg/sysemu/excp_helper.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index 796dc2a1f3..eee59aa977 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -30,8 +30,10 @@ typedef hwaddr (*MMUTranslateFunc)(CPUState *cs, hwaddr gphys, MMUAccessType acc #define GET_HPHYS(cs, gpa, access_type, prot) \ (get_hphys_func ? get_hphys_func(cs, gpa, access_type, prot) : gpa) -static int mmu_translate(CPUState *cs, hwaddr addr, MMUTranslateFunc get_hphys_func, - uint64_t cr3, int is_write1, int mmu_idx, int pg_mode, +static int mmu_translate(CPUState *cs, hwaddr addr, + MMUTranslateFunc get_hphys_func, + uint64_t cr3, MMUAccessType access_type, + int mmu_idx, int pg_mode, hwaddr *xlat, int *page_size, int *prot) { X86CPU *cpu = X86_CPU(cs); @@ -40,13 +42,13 @@ static int mmu_translate(CPUState *cs, hwaddr addr, MMUTranslateFunc get_hphys_f int32_t a20_mask; target_ulong pde_addr, pte_addr; int error_code = 0; - int is_dirty, is_write, is_user; + bool is_dirty, is_write, is_user; uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits); uint32_t page_offset; uint32_t pkr; is_user = (mmu_idx == MMU_USER_IDX); - is_write = is_write1 & 1; + is_write = (access_type == MMU_DATA_STORE); a20_mask = x86_get_a20_mask(env); if (!(pg_mode & PG_MODE_NXE)) { @@ -264,14 +266,14 @@ do_check_protect_pse36: } *prot &= pkr_prot; - if ((pkr_prot & (1 << is_write1)) == 0) { - assert(is_write1 != 2); + if ((pkr_prot & (1 << access_type)) == 0) { + assert(access_type != MMU_INST_FETCH); error_code |= PG_ERROR_PK_MASK; goto do_fault_protect; } } - if ((*prot & (1 << is_write1)) == 0) { + if ((*prot & (1 << access_type)) == 0) { goto do_fault_protect; } @@ -297,7 +299,7 @@ do_check_protect_pse36: /* align to page_size */ pte &= PG_ADDRESS_MASK & ~(*page_size - 1); page_offset = addr & (*page_size - 1); - *xlat = GET_HPHYS(cs, pte + page_offset, is_write1, prot); + *xlat = GET_HPHYS(cs, pte + page_offset, access_type, prot); return PG_ERROR_OK; do_fault_rsvd: @@ -308,7 +310,7 @@ do_check_protect_pse36: error_code |= (is_write << PG_ERROR_W_BIT); if (is_user) error_code |= PG_ERROR_U_MASK; - if (is_write1 == 2 && + if (access_type == MMU_INST_FETCH && ((pg_mode & PG_MODE_NXE) || (pg_mode & PG_MODE_SMEP))) error_code |= PG_ERROR_I_D_MASK; return error_code; @@ -353,7 +355,7 @@ hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, * 1 = generate PF fault */ static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, - int is_write1, int mmu_idx) + MMUAccessType access_type, int mmu_idx) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; @@ -365,7 +367,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, #if defined(DEBUG_MMU) printf("MMU fault: addr=%" VADDR_PRIx " w=%d mmu=%d eip=" TARGET_FMT_lx "\n", - addr, is_write1, mmu_idx, env->eip); + addr, access_type, mmu_idx, env->eip); #endif if (!(env->cr[0] & CR0_PG_MASK)) { @@ -393,7 +395,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, } } - error_code = mmu_translate(cs, addr, get_hphys, env->cr[3], is_write1, + error_code = mmu_translate(cs, addr, get_hphys, env->cr[3], access_type, mmu_idx, pg_mode, &paddr, &page_size, &prot); } @@ -404,7 +406,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, vaddr = addr & TARGET_PAGE_MASK; paddr &= TARGET_PAGE_MASK; - assert(prot & (1 << is_write1)); + assert(prot & (1 << access_type)); tlb_set_page_with_attrs(cs, vaddr, paddr, cpu_get_mem_attrs(env), prot, mmu_idx, page_size); return 0;