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([2602:ae:1598:4c01:66a6:82c2:d794:68f6]) by smtp.gmail.com with ESMTPSA id e91-20020a17090a6fe400b002508d73f4e8sm3914289pjk.57.2023.06.02.19.34.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 19:34:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ardb@kernel.org, berrange@redhat.com, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com Subject: [PATCH 10/35] crypto: Add aesdec_ISB_ISR Date: Fri, 2 Jun 2023 19:34:01 -0700 Message-Id: <20230603023426.1064431-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230603023426.1064431-1-richard.henderson@linaro.org> References: <20230603023426.1064431-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a primitive for InvSubBytes + InvShiftRows. Signed-off-by: Richard Henderson --- host/include/generic/host/aes-round.h | 3 ++ include/crypto/aes-round.h | 18 +++++++++++ crypto/aes.c | 46 +++++++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/host/include/generic/host/aes-round.h b/host/include/generic/host/aes-round.h index 598242c603..cb4fed61fe 100644 --- a/host/include/generic/host/aes-round.h +++ b/host/include/generic/host/aes-round.h @@ -12,4 +12,7 @@ void aesenc_SB_SR_accel(AESState *, const AESState *, bool) QEMU_ERROR("unsupported accel"); +void aesdec_ISB_ISR_accel(AESState *, const AESState *, bool) + QEMU_ERROR("unsupported accel"); + #endif diff --git a/include/crypto/aes-round.h b/include/crypto/aes-round.h index 784e1daee6..ff1914bd63 100644 --- a/include/crypto/aes-round.h +++ b/include/crypto/aes-round.h @@ -38,4 +38,22 @@ static inline void aesenc_SB_SR(AESState *r, const AESState *st, bool be) } } +/* + * Perform InvSubBytes + InvShiftRows. + */ + +void aesdec_ISB_ISR_gen(AESState *ret, const AESState *st); +void aesdec_ISB_ISR_genrev(AESState *ret, const AESState *st); + +static inline void aesdec_ISB_ISR(AESState *r, const AESState *st, bool be) +{ + if (HAVE_AES_ACCEL) { + aesdec_ISB_ISR_accel(r, st, be); + } else if (HOST_BIG_ENDIAN == be) { + aesdec_ISB_ISR_gen(r, st); + } else { + aesdec_ISB_ISR_genrev(r, st); + } +} + #endif /* CRYPTO_AES_ROUND_H */ diff --git a/crypto/aes.c b/crypto/aes.c index 708838315a..937377647f 100644 --- a/crypto/aes.c +++ b/crypto/aes.c @@ -1298,6 +1298,52 @@ void aesenc_SB_SR_genrev(AESState *r, const AESState *st) aesenc_SB_SR_swap(r, st, true); } +/* Perform InvSubBytes + InvShiftRows. */ +static inline void +aesdec_ISB_ISR_swap(AESState *r, const AESState *st, bool swap) +{ + const int swap_b = swap ? 15 : 0; + uint8_t t; + + /* These four indexes are not swizzled. */ + r->b[swap_b ^ 0x0] = AES_isbox[st->b[swap_b ^ AES_ISH_0]]; + r->b[swap_b ^ 0x4] = AES_isbox[st->b[swap_b ^ AES_ISH_4]]; + r->b[swap_b ^ 0x8] = AES_isbox[st->b[swap_b ^ AES_ISH_8]]; + r->b[swap_b ^ 0xc] = AES_isbox[st->b[swap_b ^ AES_ISH_C]]; + + /* Otherwise, break cycles. */ + + t = AES_isbox[st->b[swap_b ^ AES_ISH_5]]; + r->b[swap_b ^ 0x1] = AES_isbox[st->b[swap_b ^ AES_ISH_1]]; + r->b[swap_b ^ 0xd] = AES_isbox[st->b[swap_b ^ AES_ISH_D]]; + r->b[swap_b ^ 0x9] = AES_isbox[st->b[swap_b ^ AES_ISH_9]]; + r->b[swap_b ^ 0x5] = t; + + t = AES_isbox[st->b[swap_b ^ AES_ISH_A]]; + r->b[swap_b ^ 0x2] = AES_isbox[st->b[swap_b ^ AES_ISH_2]]; + r->b[swap_b ^ 0xa] = t; + + t = AES_isbox[st->b[swap_b ^ AES_ISH_E]]; + r->b[swap_b ^ 0x6] = AES_isbox[st->b[swap_b ^ AES_ISH_6]]; + r->b[swap_b ^ 0xe] = t; + + t = AES_isbox[st->b[swap_b ^ AES_ISH_F]]; + r->b[swap_b ^ 0x3] = AES_isbox[st->b[swap_b ^ AES_ISH_3]]; + r->b[swap_b ^ 0x7] = AES_isbox[st->b[swap_b ^ AES_ISH_7]]; + r->b[swap_b ^ 0xb] = AES_isbox[st->b[swap_b ^ AES_ISH_B]]; + r->b[swap_b ^ 0xf] = t; +} + +void aesdec_ISB_ISR_gen(AESState *r, const AESState *st) +{ + aesdec_ISB_ISR_swap(r, st, false); +} + +void aesdec_ISB_ISR_genrev(AESState *r, const AESState *st) +{ + aesdec_ISB_ISR_swap(r, st, true); +} + /** * Expand the cipher key into the encryption key schedule. */