| Message ID | 20230719153018.1456180-4-jean-philippe@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Fixes for RME | expand |
On Wed, 19 Jul 2023 at 16:56, Jean-Philippe Brucker <jean-philippe@linaro.org> wrote: > > When HCR_EL2.E2H is enabled, TLB entries are formed using the EL2&0 > translation regime, instead of the EL2 translation regime. The TLB VAE2* > instructions invalidate the regime that corresponds to the current value > of HCR_EL2.E2H. > > At the moment we only invalidate the EL2 translation regime. This causes > problems with RMM, which issues TLBI VAE2IS instructions with > HCR_EL2.E2H enabled. Update vae2_tlbmask() to take HCR_EL2.E2H into > account. > > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> > --- > target/arm/helper.c | 26 ++++++++++++++++++-------- > 1 file changed, 18 insertions(+), 8 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index e1b3db6f5f..07a9ac70f5 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -4663,6 +4663,21 @@ static int vae1_tlbmask(CPUARMState *env) > return mask; > } > > +static int vae2_tlbmask(CPUARMState *env) > +{ > + uint64_t hcr = arm_hcr_el2_eff(env); > + uint16_t mask; > + > + if (hcr & HCR_E2H) { > + mask = ARMMMUIdxBit_E20_2 | > + ARMMMUIdxBit_E20_2_PAN | > + ARMMMUIdxBit_E20_0; > + } else { > + mask = ARMMMUIdxBit_E2; > + } > + return mask; > +} > + > /* Return 56 if TBI is enabled, 64 otherwise. */ > static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, > uint64_t addr) > @@ -4838,11 +4853,11 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > CPUState *cs = env_cpu(env); > + int mask = vae2_tlbmask(env); > uint64_t pageaddr = sextract64(value << 12, 0, 56); > int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); Shouldn't the argument to tlbbits_for_regime() also change if we're dealing with the EL2&0 regime rather than EL2 ? > > - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, > - ARMMMUIdxBit_E2, bits); > + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); > } thanks -- PMM
On Thu, Jul 20, 2023 at 05:35:49PM +0100, Peter Maydell wrote: > On Wed, 19 Jul 2023 at 16:56, Jean-Philippe Brucker > <jean-philippe@linaro.org> wrote: > > > > When HCR_EL2.E2H is enabled, TLB entries are formed using the EL2&0 > > translation regime, instead of the EL2 translation regime. The TLB VAE2* > > instructions invalidate the regime that corresponds to the current value > > of HCR_EL2.E2H. > > > > At the moment we only invalidate the EL2 translation regime. This causes > > problems with RMM, which issues TLBI VAE2IS instructions with > > HCR_EL2.E2H enabled. Update vae2_tlbmask() to take HCR_EL2.E2H into > > account. > > > > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> > > --- > > target/arm/helper.c | 26 ++++++++++++++++++-------- > > 1 file changed, 18 insertions(+), 8 deletions(-) > > > > diff --git a/target/arm/helper.c b/target/arm/helper.c > > index e1b3db6f5f..07a9ac70f5 100644 > > --- a/target/arm/helper.c > > +++ b/target/arm/helper.c > > @@ -4663,6 +4663,21 @@ static int vae1_tlbmask(CPUARMState *env) > > return mask; > > } > > > > +static int vae2_tlbmask(CPUARMState *env) > > +{ > > + uint64_t hcr = arm_hcr_el2_eff(env); > > + uint16_t mask; > > + > > + if (hcr & HCR_E2H) { > > + mask = ARMMMUIdxBit_E20_2 | > > + ARMMMUIdxBit_E20_2_PAN | > > + ARMMMUIdxBit_E20_0; > > + } else { > > + mask = ARMMMUIdxBit_E2; > > + } > > + return mask; > > +} > > + > > /* Return 56 if TBI is enabled, 64 otherwise. */ > > static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, > > uint64_t addr) > > > @@ -4838,11 +4853,11 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, > > uint64_t value) > > { > > CPUState *cs = env_cpu(env); > > + int mask = vae2_tlbmask(env); > > uint64_t pageaddr = sextract64(value << 12, 0, 56); > > int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); > > Shouldn't the argument to tlbbits_for_regime() also change > if we're dealing with the EL2&0 regime rather than EL2 ? Yes, it affects the result since EL2&0 has two ranges Thanks, Jean > > > > > - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, > > - ARMMMUIdxBit_E2, bits); > > + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); > > } > > thanks > -- PMM
diff --git a/target/arm/helper.c b/target/arm/helper.c index e1b3db6f5f..07a9ac70f5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4663,6 +4663,21 @@ static int vae1_tlbmask(CPUARMState *env) return mask; } +static int vae2_tlbmask(CPUARMState *env) +{ + uint64_t hcr = arm_hcr_el2_eff(env); + uint16_t mask; + + if (hcr & HCR_E2H) { + mask = ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; + } else { + mask = ARMMMUIdxBit_E2; + } + return mask; +} + /* Return 56 if TBI is enabled, 64 otherwise. */ static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr) @@ -4781,7 +4796,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, * flush-last-level-only. */ CPUState *cs = env_cpu(env); - int mask = e2_tlbmask(env); + int mask = vae2_tlbmask(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); tlb_flush_page_by_mmuidx(cs, pageaddr, mask); @@ -4838,11 +4853,11 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs = env_cpu(env); + int mask = vae2_tlbmask(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_E2, bits); + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); } static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -5014,11 +5029,6 @@ static void tlbi_aa64_rvae1is_write(CPUARMState *env, do_rvae_write(env, value, vae1_tlbmask(env), true); } -static int vae2_tlbmask(CPUARMState *env) -{ - return ARMMMUIdxBit_E2; -} - static void tlbi_aa64_rvae2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
When HCR_EL2.E2H is enabled, TLB entries are formed using the EL2&0 translation regime, instead of the EL2 translation regime. The TLB VAE2* instructions invalidate the regime that corresponds to the current value of HCR_EL2.E2H. At the moment we only invalidate the EL2 translation regime. This causes problems with RMM, which issues TLBI VAE2IS instructions with HCR_EL2.E2H enabled. Update vae2_tlbmask() to take HCR_EL2.E2H into account. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> --- target/arm/helper.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-)