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[176.131.223.129]) by smtp.gmail.com with ESMTPSA id ba30-20020a0564021ade00b00525c01f91b0sm1315928edb.42.2023.09.14.12.52.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 14 Sep 2023 12:52:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Greg Kurz , Anton Johansson , Yanan Wang , Richard Henderson , David Gibson , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , Marcel Apfelbaum , Daniel Henrique Barboza , =?utf-8?q?Alex_Benn=C3=A9e?= , Paolo Bonzini , Harsh Prateek Bora , qemu-ppc@nongnu.org Subject: [RFC PATCH 3/4] accel/tcg: Guard tb_flush() with tcg_enabled() and remove the stub Date: Thu, 14 Sep 2023 21:52:28 +0200 Message-ID: <20230914195229.78244-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230914195229.78244-1-philmd@linaro.org> References: <20230914195229.78244-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philmd@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The check on tcg_enabled() make it clearer we want this call under TCG. Signed-off-by: Philippe Mathieu-Daudé --- accel/stubs/tcg-stub.c | 4 ---- cpu.c | 15 +++++++++------ gdbstub/softmmu.c | 5 ++++- hw/ppc/spapr_hcall.c | 2 +- 4 files changed, 14 insertions(+), 12 deletions(-) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index dd890d6cf6..7d9846f7f2 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -14,10 +14,6 @@ #include "exec/tb-flush.h" #include "exec/exec-all.h" -void tb_flush(CPUState *cpu) -{ -} - int probe_access_flags(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) diff --git a/cpu.c b/cpu.c index 0769b0b153..ce3b04f21f 100644 --- a/cpu.c +++ b/cpu.c @@ -57,12 +57,15 @@ static int cpu_common_post_load(void *opaque, int version_id) cpu->interrupt_request &= ~0x01; tlb_flush(cpu); - /* loadvm has just updated the content of RAM, bypassing the - * usual mechanisms that ensure we flush TBs for writes to - * memory we've translated code from. So we must flush all TBs, - * which will now be stale. - */ - tb_flush(cpu); + if (tcg_enabled()) { + /* + * loadvm has just updated the content of RAM, bypassing the + * usual mechanisms that ensure we flush TBs for writes to + * memory we've translated code from. So we must flush all TBs, + * which will now be stale. + */ + tb_flush(cpu); + } return 0; } diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index 9f0b8b5497..edd13f047d 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -21,6 +21,7 @@ #include "sysemu/cpus.h" #include "sysemu/runstate.h" #include "sysemu/replay.h" +#include "sysemu/tcg.h" #include "hw/core/cpu.h" #include "hw/cpu/cluster.h" #include "hw/boards.h" @@ -170,7 +171,9 @@ static void gdb_vm_state_change(void *opaque, bool running, RunState state) } else { trace_gdbstub_hit_break(); } - tb_flush(cpu); + if (tcg_enabled()) { + tb_flush(cpu); + } ret = GDB_SIGNAL_TRAP; break; case RUN_STATE_PAUSED: diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index b7dc388f2f..306f8fdf55 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -296,7 +296,7 @@ static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { if (kvm_enabled()) { kvmppc_icbi_range(cpu, pdst, len); - } else { + } else if (tcg_enabled()) { tb_flush(CPU(cpu)); } }