[v3,29/38] tcg/sparc64: Support TCG_COND_TST{EQ,NE}

Message ID	20240110224408.10444-30-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v3 29/38] tcg/sparc64: Support TCG_COND_TST{EQ,NE} Date: Thu, 11 Jan 2024 09:43:59 +1100 Message-Id: <20240110224408.10444-30-richard.henderson@linaro.org> In-Reply-To: <20240110224408.10444-1-richard.henderson@linaro.org> References: <20240110224408.10444-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::82b; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	tcg: Introduce TCG_COND_TST{EQ,NE} \| expand [v3,00/38] tcg: Introduce TCG_COND_TST{EQ,NE} [v3,01/38] tcg: Introduce TCG_COND_TST{EQ,NE} [v3,02/38] tcg: Introduce TCG_TARGET_HAS_tst [v3,03/38] tcg/optimize: Split out arg_is_const_val [v3,04/38] tcg/optimize: Split out do_constant_folding_cond1 [v3,05/38] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 [v3,06/38] tcg/optimize: Handle TCG_COND_TST{EQ,NE} [v3,07/38] tcg/optimize: Lower TCG_COND_TST{EQ, NE} if unsupported [v3,08/38] target/alpha: Pass immediate value to gen_bcond_internal() [v3,09/38] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} [v3,10/38] target/alpha: Use TCG_COND_TST{EQ, NE} for CMOVLB{C, S} [v3,11/38] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero [v3,12/38] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond [v3,13/38] target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc [v3,14/38] target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM} [v3,15/38] target/s390x: Improve general case of disas_jcc [v3,16/38] tcg: Add TCGConst argument to tcg_target_const_match [v3,17/38] tcg/aarch64: Support TCG_COND_TST{EQ,NE} [v3,18/38] tcg/aarch64: Generate TBZ, TBNZ [v3,19/38] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX [v3,20/38] tcg/arm: Factor tcg_out_cmp() out [v3,21/38] tcg/arm: Support TCG_COND_TST{EQ,NE} [v3,22/38] tcg/i386: Pass x86 condition codes to tcg_out_cmov [v3,23/38] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp [v3,24/38] tcg/i386: Support TCG_COND_TST{EQ,NE} [v3,25/38] tcg/i386: Improve TSTNE/TESTEQ vs powers of two [v3,26/38] tcg/i386: Use TEST r,r to test 8/16/32 bits [v3,27/38] tcg/sparc64: Hoist read of tcg_cond_to_rcond [v3,28/38] tcg/sparc64: Pass TCGCond to tcg_out_cmp [v3,29/38] tcg/sparc64: Support TCG_COND_TST{EQ,NE} [v3,30/38] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc [v3,31/38] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel [v3,32/38] tcg/ppc: Tidy up tcg_target_const_match [v3,33/38] tcg/ppc: Add TCG_CT_CONST_CMP [v3,34/38] tcg/ppc: Support TCG_COND_TST{EQ,NE} [v3,35/38] tcg/s390x: Split constraint A into J+U [v3,36/38] tcg/s390x: Add TCG_CT_CONST_CMP [v3,37/38] tcg/s390x: Support TCG_COND_TST{EQ,NE} [v3,38/38] tcg/tci: Support TCG_COND_TST{EQ,NE}

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20240110224408.10444-30-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
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	pbonzini@redhat.com
Subject: [PATCH v3 29/38] tcg/sparc64: Support TCG_COND_TST{EQ,NE}
Date: Thu, 11 Jan 2024 09:43:59 +1100
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Series

tcg: Introduce TCG_COND_TST{EQ,NE} | expand

Commit Message

Richard Henderson Jan. 10, 2024, 10:43 p.m. UTC

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/sparc64/tcg-target.h     |  2 +-
 tcg/sparc64/tcg-target.c.inc | 16 ++++++++++++++--
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h
index ae2910c4ee..a18906a14e 100644
--- a/tcg/sparc64/tcg-target.h
+++ b/tcg/sparc64/tcg-target.h
@@ -149,7 +149,7 @@  extern bool use_vis3_instructions;
 
 #define TCG_TARGET_HAS_qemu_ldst_i128   0
 
-#define TCG_TARGET_HAS_tst              0
+#define TCG_TARGET_HAS_tst              1
 
 #define TCG_AREG0 TCG_REG_I0
 
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 10fb8a1a0d..176c98740b 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -607,9 +607,11 @@  static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1,
                    uns ? ARITH_UDIV : ARITH_SDIV);
 }
 
-static const uint8_t tcg_cond_to_bcond[] = {
+static const uint8_t tcg_cond_to_bcond[16] = {
     [TCG_COND_EQ] = COND_E,
     [TCG_COND_NE] = COND_NE,
+    [TCG_COND_TSTEQ] = COND_E,
+    [TCG_COND_TSTNE] = COND_NE,
     [TCG_COND_LT] = COND_L,
     [TCG_COND_GE] = COND_GE,
     [TCG_COND_LE] = COND_LE,
@@ -649,7 +651,8 @@  static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l)
 static void tcg_out_cmp(TCGContext *s, TCGCond cond,
                         TCGReg c1, int32_t c2, int c2const)
 {
-    tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
+    tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const,
+                   is_tst_cond(cond) ? ARITH_ANDCC : ARITH_SUBCC);
 }
 
 static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1,
@@ -744,6 +747,15 @@  static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
         cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
 	break;
 
+    case TCG_COND_TSTEQ:
+    case TCG_COND_TSTNE:
+        /* Transform to inequality vs zero.  */
+        tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_AND);
+        c1 = TCG_REG_G0;
+        c2 = TCG_REG_T1, c2const = 0;
+        cond = (cond == TCG_COND_TSTEQ ? TCG_COND_GEU : TCG_COND_LTU);
+	break;
+
     case TCG_COND_GTU:
     case TCG_COND_LEU:
         /* If we don't need to load a constant into a register, we can

[v3,29/38] tcg/sparc64: Support TCG_COND_TST{EQ,NE}

Commit Message

Patch