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[PULL,24/43] target/hppa: Use TCG_COND_TST* in trans_bb_imm

Message ID 20240515094043.82850-25-richard.henderson@linaro.org
State Accepted
Commit b041ec9d7173ec893c1a5bc0bfd25fe860b4fcb0
Headers show
Series [PULL,01/43] target/hppa: Move cpu_get_tb_cpu_state out of line | expand

Commit Message

Richard Henderson May 15, 2024, 9:40 a.m. UTC 
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/translate.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)
diff mbox series

Patch

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4e49bd2b67..af6be5100c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3516,18 +3516,12 @@  static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
 
 static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
 {
-    TCGv_i64 tmp, tcg_r;
     DisasCond cond;
-    int p;
+    int p = a->p | (a->d ? 0 : 32);
 
     nullify_over(ctx);
-
-    tmp = tcg_temp_new_i64();
-    tcg_r = load_gpr(ctx, a->r);
-    p = a->p | (a->d ? 0 : 32);
-    tcg_gen_shli_i64(tmp, tcg_r, p);
-
-    cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0);
+    cond = cond_make_vi(a->c ? TCG_COND_TSTEQ : TCG_COND_TSTNE,
+                        load_gpr(ctx, a->r), 1ull << (63 - p));
     return do_cbranch(ctx, a->disp, a->n, &cond);
 }