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[209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-795183eb40dsi115666385a.329.2024.06.04.02.57.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jun 2024 02:57:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NAOqbAZ9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sEQu2-0005Jc-VE; Tue, 04 Jun 2024 05:56:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sEQu1-0005J7-Rk for qemu-devel@nongnu.org; Tue, 04 Jun 2024 05:56:26 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sEQu0-00022D-7O for qemu-devel@nongnu.org; Tue, 04 Jun 2024 05:56:25 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-42137366995so34379345e9.3 for ; Tue, 04 Jun 2024 02:56:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717494982; x=1718099782; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2Ay+Vb25Ah58Dvvnz7p7zDrtYiMbYdEQ6V3ef1gToK4=; b=NAOqbAZ9rXscGu3Fo7xbmPVgkeZ9s/+ZuBzZJ5F7mW3ba9mMw8NOxkLNZlQmHV2F47 meV0OOq0IvtlNV8o+61z4+HhD5amDZsdVCwv4z0/8hDt864ahNwNlW+27VyG44lNPZWk 7Av4VmzUxZMgS9YPzI2gV8db+reyrO1Fv12y+CScxO2sonfOSiC41V8XwgViWZ9dvGOP luWNFRBcyh+ma52HYL3BiWjpuPpXkCZH/Kgna3WvgM0QtA95JIixfWEeLZzpL6AbQoP9 BTyNr1Ouwhsw+dEG7CCuXwMY8U7sroRkn3rD5qKCgPm4hxWs/hlk3RTCo9NFOQBkc6H1 NynQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717494982; x=1718099782; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Ay+Vb25Ah58Dvvnz7p7zDrtYiMbYdEQ6V3ef1gToK4=; b=NMz15+YlDtZFxrkZLcyzVWVw3BLObXncExJqqAwPGb5LtiBp57/WzQtMqWZABoxEas Uk0CB4uxAxl246z7RMTEVStZh9yVl94PFjDOKHw4fPzg3xKGF3gkIWoTz7+iAw1ZGSag 2jaYBi65Vt1x+bAJlpzM95DEco5UlF+DFUt+QGRfoC/n3KIMNpULCBeukzngFoeAODs/ oEGhVcqYuw87lN2TIqx2Zd0aD7Thy6LrWMC/JUZq6xcL7B4ikiAl1bmz669Ngp3ocH+J CEaAaEHDwC/L8YHe5trUoxe8r+8nHRpOoLsb+1mEbi+nuMuclH7fRQFfBjgQmnwKAcCU 4ADw== X-Gm-Message-State: AOJu0Yxeo8EvlyoBEh1VPim7096yhSNpIqEuVnUuwCPbv8AtNkmioabO lBDbuv15512wb8qtAOj77f2ATrUhMYwkRUJeRDa374XNR3qhhibvZvWRm2U4tfnl6kEPE3EWpXr E X-Received: by 2002:a05:600c:5248:b0:421:4ecb:bd68 with SMTP id 5b1f17b1804b1-4214ecbbf7amr14446145e9.31.1717494982345; Tue, 04 Jun 2024 02:56:22 -0700 (PDT) Received: from m1x-phil.lan ([176.176.159.34]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35dd062edbcsm11070738f8f.84.2024.06.04.02.56.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jun 2024 02:56:21 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 02/32] target/riscv: Restrict 'rv128' machine to TCG accelerator Date: Tue, 4 Jun 2024 11:55:38 +0200 Message-ID: <20240604095609.12285-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240604095609.12285-1-philmd@linaro.org> References: <20240604095609.12285-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We only build for 32/64-bit hosts, so TCG is required for 128-bit targets. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-Id: <20230626232007.8933-5-philmd@linaro.org> --- target/riscv/cpu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eb1a2e7d6d..0dad66ec96 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -591,6 +591,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } +#ifdef CONFIG_TCG static void rv128_base_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); @@ -612,6 +613,7 @@ static void rv128_base_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif } +#endif /* CONFIG_TCG */ static void rv64i_bare_cpu_init(Object *obj) { @@ -624,7 +626,9 @@ static void rv64e_bare_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; riscv_cpu_set_misa_ext(env, RVE); } -#else + +#else /* !TARGET_RISCV64 */ + static void rv32_base_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); @@ -2550,12 +2554,14 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init), +#ifdef CONFIG_TCG DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init), +#endif /* CONFIG_TCG */ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init), -#endif +#endif /* TARGET_RISCV64 */ }; DEFINE_TYPES(riscv_cpu_type_infos)