[PULL,11/38] target/sparc: Add feature bits for VIS 3

Message ID	20240605172253.356302-12-richard.henderson@linaro.org
State	Accepted
Commit	3335a04806d337c69f44a707cdc27515d6c91d84
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PULL 11/38] target/sparc: Add feature bits for VIS 3 Date: Wed, 5 Jun 2024 10:22:26 -0700 Message-Id: <20240605172253.356302-12-richard.henderson@linaro.org> In-Reply-To: <20240605172253.356302-1-richard.henderson@linaro.org> References: <20240605172253.356302-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/38] linux-user: Add ioctl for BLKBSZSET \| expand [PULL,01/38] linux-user: Add ioctl for BLKBSZSET [PULL,02/38] target/sparc: Fix ARRAY8 [PULL,03/38] target/sparc: Rewrite gen_edge [PULL,04/38] target/sparc: Fix do_dc [PULL,05/38] target/sparc: Fix helper_fmul8ulx16 [PULL,06/38] target/sparc: Perform DFPREG/QFPREG in decodetree [PULL,07/38] target/sparc: Remove gen_dest_fpr_D [PULL,08/38] target/sparc: Remove cpu_fpr[] [PULL,09/38] target/sparc: Use gvec for VIS1 parallel add/sub [PULL,10/38] target/sparc: Implement FMAf extension [PULL,11/38] target/sparc: Add feature bits for VIS 3 [PULL,12/38] target/sparc: Implement ADDXC, ADDXCcc [PULL,13/38] target/sparc: Implement CMASK instructions [PULL,14/38] target/sparc: Implement FCHKSM16 [PULL,15/38] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL [PULL,16/38] target/sparc: Implement FLCMP [PULL,17/38] target/sparc: Implement FMEAN16 [PULL,18/38] target/sparc: Implement FPADD64, FPSUB64 [PULL,19/38] target/sparc: Implement FPADDS, FPSUBS [PULL,20/38] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 [PULL,21/38] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS [PULL,22/38] target/sparc: Implement LDXEFSR [PULL,23/38] target/sparc: Implement LZCNT [PULL,24/38] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd [PULL,25/38] target/sparc: Implement PDISTN [PULL,26/38] target/sparc: Implement UMULXHI [PULL,27/38] target/sparc: Implement XMULX [PULL,28/38] target/sparc: Enable VIS3 feature bit [PULL,29/38] target/sparc: Implement IMA extension [PULL,30/38] target/sparc: Add feature bit for VIS4 [PULL,31/38] target/sparc: Implement FALIGNDATAi [PULL,32/38] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS [PULL,33/38] target/sparc: Implement VIS4 comparisons [PULL,34/38] target/sparc: Implement FPMIN, FPMAX [PULL,35/38] target/sparc: Implement SUBXC, SUBXCcc [PULL,36/38] target/sparc: Implement MWAIT [PULL,37/38] target/sparc: Implement monitor ASIs [PULL,38/38] target/sparc: Enable VIS4 feature bit

Message ID

20240605172253.356302-12-richard.henderson@linaro.org

State

Accepted

Commit

3335a04806d337c69f44a707cdc27515d6c91d84

Headers

Received-SPF: pass (google.com: domain of
 qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as
 permitted sender) client-ip=209.51.188.17;
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PULL 11/38] target/sparc: Add feature bits for VIS 3
Date: Wed,  5 Jun 2024 10:22:26 -0700
Message-Id: <20240605172253.356302-12-richard.henderson@linaro.org>
In-Reply-To: <20240605172253.356302-1-richard.henderson@linaro.org>
References: <20240605172253.356302-1-richard.henderson@linaro.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Received-SPF: pass client-ip=2607:f8b0:4864:20::432;
 envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com
X-Spam_score_int: -20
X-Spam_score: -2.1
X-Spam_bar: --
X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,
 DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,
 RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,
 T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no
X-Spam_action: no action
X-BeenThere: qemu-devel@nongnu.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
 <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
 <mailto:qemu-devel-request@nongnu.org?subject=subscribe>
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org

Series

[PULL,01/38] linux-user: Add ioctl for BLKBSZSET | expand

Commit Message

Richard Henderson June 5, 2024, 5:22 p.m. UTC

The manual separates VIS 3 and VIS 3B, even though they are both
present in all extant cpus.  For clarity, let the translator
match the manual but otherwise leave them on the same feature bit.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/cpu-feature.h.inc | 1 +
 target/sparc/translate.c       | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc
index a30b9255b2..3913fb4a54 100644
--- a/target/sparc/cpu-feature.h.inc
+++ b/target/sparc/cpu-feature.h.inc
@@ -13,3 +13,4 @@  FEATURE(CACHE_CTRL)
 FEATURE(POWERDOWN)
 FEATURE(CASA)
 FEATURE(FMAF)
+FEATURE(VIS3)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 5efd09f4f4..59b922c903 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2188,6 +2188,8 @@  static int extract_qfpreg(DisasContext *dc, int x)
 # define avail_HYPV(C)    ((C)->def->features & CPU_FEATURE_HYPV)
 # define avail_VIS1(C)    ((C)->def->features & CPU_FEATURE_VIS1)
 # define avail_VIS2(C)    ((C)->def->features & CPU_FEATURE_VIS2)
+# define avail_VIS3(C)    ((C)->def->features & CPU_FEATURE_VIS3)
+# define avail_VIS3B(C)   avail_VIS3(C)
 #else
 # define avail_32(C)      true
 # define avail_ASR17(C)   ((C)->def->features & CPU_FEATURE_ASR17)
@@ -2201,6 +2203,8 @@  static int extract_qfpreg(DisasContext *dc, int x)
 # define avail_HYPV(C)    false
 # define avail_VIS1(C)    false
 # define avail_VIS2(C)    false
+# define avail_VIS3(C)    false
+# define avail_VIS3B(C)   false
 #endif
 
 /* Default case for non jump instructions. */

[PULL,11/38] target/sparc: Add feature bits for VIS 3

Commit Message

Patch