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Wed, 11 Sep 2024 05:20:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PULL 51/56] hw/pci-host: remove break after g_assert_not_reached() Date: Wed, 11 Sep 2024 14:14:16 +0200 Message-ID: <20240911121422.52585-52-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240911121422.52585-1-philmd@linaro.org> References: <20240911121422.52585-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Pierrick Bouvier Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240910221606.1817478-31-pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/gt64120.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index 33607dfbec..5855741662 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -689,7 +689,6 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_PCI0_CFGDATA: /* Mapped via in gt64120_pci_mapping() */ g_assert_not_reached(); - break; /* Interrupts */ case GT_INTRCAUSE: @@ -933,7 +932,6 @@ static uint64_t gt64120_readl(void *opaque, case GT_PCI0_CFGDATA: /* Mapped via in gt64120_pci_mapping() */ g_assert_not_reached(); - break; case GT_PCI0_CMD: case GT_PCI0_TOR: