From patchwork Sat Oct 5 15:25:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 832970 Delivered-To: patch@linaro.org Received: by 2002:adf:8b52:0:b0:367:895a:4699 with SMTP id v18csp1255586wra; Sat, 5 Oct 2024 08:26:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVj1ke+x70O31fzCAI66z6wSRKjluJSmx8DiEVLStLpcRyldh2DRyU+j21l/VPZisot3eNN9Q==@linaro.org X-Google-Smtp-Source: AGHT+IHAsxw1Ia4cBJlzuoA4hORx5apueNt2708cERrx3+7n10CrqTj1vizotb3lhvk8qtaxUnCG X-Received: by 2002:a05:622a:1ba5:b0:458:2c22:e696 with SMTP id d75a77b69052e-45d9bb2a884mr83834051cf.56.1728141995098; Sat, 05 Oct 2024 08:26:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1728141995; cv=none; d=google.com; s=arc-20240605; b=O2Sz9+O1WD0AgPfqn1Z9yjcCrmeRqY4L1VNYStt/76ZynX9gQoaCb8SbqnseyWHaZU R2aVZzEtUlkHpd3Zxll8N/4yKCeXP7ETLtGdgX0cclySqi1Yw2noEWp1g04C/BZiJaF6 CpT8BOF0uw0tZaWPNQKXXop1lSxm72TJ2Q3eDL1nEPNy/UBLIjMFHxqdEUGmHgf6Yh3B xmAe8GDo07Tsegn5JUlfLEqgInJ8dykdE76iGnTbDD7fjj5siN8kjQRCRzC5gfSRyoJA fmbC7Cw4W/yUT8HJwcVcQHrRqoLUxzWkFbkKXkcKFhV0DIMU6yWEI0RxUVyaaoy6qVAQ nK+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qIlBHpyIHO+kiCFyGgZVBXgacr4yw5gCrMn63zUSz3U=; fh=rQg8EQ8KH04w/0VkDYF6/ktgEyHJ2dqn1eatHCfBaLw=; b=RU1axX2j2WY/q2fZ2QYpWTNLH1x2jyFIQr29OacHdA6Axi0rVpVIMN0kTFZBGLr++J AcEjHLA6Eo0Y4gHio/L6uerK+xHbnPVS5aswZgnUiYhGIfuS9m3EZ1/tPAfwC/gHo4rm P+hdD+2RwA0wsMOgxU9nppcwnfh0biZMmDEhpiPW+UQuWn+3Xl/Ke0EHZBv/Qjb6y+uq Rt87saY02T0+VY7nz+PqnF5H6x0mGnTJ5R1rDAJ8IyPkIethOHR4w6XZV5UF7H1KqA2y PFOFcJDcTp070LQwGQoAYLMywJmRKexZCSyLmYx/9USdv2AfgOFf18J6cygC7qk/cHc1 BeXQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eDMItdVM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-45da74e5eacsi21406401cf.202.2024.10.05.08.26.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 05 Oct 2024 08:26:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eDMItdVM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sx6fj-0002Cg-Sq; Sat, 05 Oct 2024 11:26:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sx6ff-0002AA-Hh for qemu-devel@nongnu.org; Sat, 05 Oct 2024 11:26:15 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sx6fd-0002Qt-Jl for qemu-devel@nongnu.org; Sat, 05 Oct 2024 11:26:15 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-20b95359440so27109595ad.0 for ; Sat, 05 Oct 2024 08:26:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728141972; x=1728746772; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qIlBHpyIHO+kiCFyGgZVBXgacr4yw5gCrMn63zUSz3U=; b=eDMItdVME/VsMLfCoup7x9FWV5tSbBjc2rTrL3G3ZRO7H97Uwh6WV8kZY98RIWxYVz 0LQe7c9kLru7UOTrQFY7W70Or/R9UMzquKSYRy0WwJPdFtVTOf44zds9NmL9Q6xt05/f YAwFMkxdOmAiXSt/11m8K/uNVG7NTo7+HsySX2Vsc0Dlwt2UZRHDeIq3YZ9Nwreg2qT/ G98b+nQhKzYdtYuIDD/zJdwVpIr/AMwUhOxB7neBWLkpbALAPQwDBcp8slJ2tiy7nc4J BijDdZZfpr5+pp7w+w5H/o3gXS0afn0LVidyoUzcMV42KvGFhuNr8XlDz0UGcx7pKK// y93Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728141972; x=1728746772; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qIlBHpyIHO+kiCFyGgZVBXgacr4yw5gCrMn63zUSz3U=; b=YDan9tVefdTHkpPZDIeXV7XSC8RtDZnpw6FNTD3sbaMUMGd+tnsmlFGBEmn8CmuqjV kqEJigEZQLrtzNviyNTelYUmrciprEfObQ5jhuEB7tnL87LRZGfvoRXfuHUbUazIM7t9 d7/wRtsbiUqTLqvL7huzZ7XeEcZerKTeJyEk8/uj+DasEAQKT7EArYdaM8ewOHJkz3pS XP2/SvF3EbiGDNTrHt2ikDjRbQwHNUM2lW2gp6KGhrC7oNpHSlsPOxEBZDD2oMqhz9UF fQ1GLW0/jlACzD3yF1p09KKyrehhgOAQ9sKf8J4MIz1dvFhsv7V1tye8L/Zv0UMeipz1 hVtw== X-Gm-Message-State: AOJu0YyTqW26ldEfwVbeSvCik+YYB4fvVAt+pxVtNEI/CuqE1uSCbyyA IhGOUf0/EvINS+hkrBUoDMQJGjNxFJ5xk6icS4jwrjc5I/tKf0mO3qxR0vWcxa4R3AfeHwYEYdF t X-Received: by 2002:a17:902:d2d1:b0:20b:9547:9b2d with SMTP id d9443c01a7336-20bfde55510mr91868295ad.2.1728141972285; Sat, 05 Oct 2024 08:26:12 -0700 (PDT) Received: from stoup.. (174-21-81-121.tukw.qwest.net. [174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:26:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 20/20] target/arm: Fix alignment fault priority in get_phys_addr_lpae Date: Sat, 5 Oct 2024 08:25:51 -0700 Message-ID: <20241005152551.307923-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org> References: <20241005152551.307923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that we have the MemOp for the access, we can order the alignment fault caused by memory type before the permission fault for the page. For subsequent page hits, permission and stage 2 checks are known to pass, and so the TLB_CHECK_ALIGNED fault raised in generic code is not mis-ordered. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 49 +++++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0a1a820362..50aa5e338c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2129,6 +2129,34 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, device = S1_attrs_are_device(result->cacheattrs.attrs); } + /* + * Enable alignment checks on Device memory. + * + * Per R_XCHFJ, the correct ordering for alignment, permission, + * and stage 2 faults is: + * - Alignment fault caused by the memory type + * - Permission fault + * - A stage 2 fault on the memory access + * Perform the alignment check now, so that we recognize it in + * the correct order. Set TLB_CHECK_ALIGNED so that any subsequent + * softmmu tlb hit will also check the alignment. + * + * In v7, for a CPU without the Virtualization Extensions this + * access is UNPREDICTABLE; we choose to make it take the alignment + * fault as is required for a v7VE CPU. (QEMU doesn't emulate any + * CPUs with ARM_FEATURE_LPAE but not ARM_FEATURE_V7VE anyway.) + */ + if (device) { + unsigned a_bits = memop_atomicity_bits(memop); + if (address & ((1 << a_bits) - 1)) { + fi->type = ARMFault_Alignment; + goto do_fault; + } + result->f.tlb_fill_flags = TLB_CHECK_ALIGNED; + } else { + result->f.tlb_fill_flags = 0; + } + if (!(result->f.prot & (1 << access_type))) { fi->type = ARMFault_Permission; goto do_fault; @@ -2156,27 +2184,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, result->f.attrs.space = out_space; result->f.attrs.secure = arm_space_is_secure(out_space); - /* - * Enable alignment checks on Device memory. - * - * Per R_XCHFJ, this check is mis-ordered. The correct ordering - * for alignment, permission, and stage 2 faults should be: - * - Alignment fault caused by the memory type - * - Permission fault - * - A stage 2 fault on the memory access - * but due to the way the TCG softmmu TLB operates, we will have - * implicitly done the permission check and the stage2 lookup in - * finding the TLB entry, so the alignment check cannot be done sooner. - * - * In v7, for a CPU without the Virtualization Extensions this - * access is UNPREDICTABLE; we choose to make it take the alignment - * fault as is required for a v7VE CPU. (QEMU doesn't emulate any - * CPUs with ARM_FEATURE_LPAE but not ARM_FEATURE_V7VE anyway.) - */ - if (device) { - result->f.tlb_fill_flags |= TLB_CHECK_ALIGNED; - } - /* * For FEAT_LPA2 and effective DS, the SH field in the attributes * was re-purposed for output address bits. The SH attribute in