From patchwork Fri Nov 1 17:08:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierrick Bouvier X-Patchwork-Id: 840107 Delivered-To: patch@linaro.org Received: by 2002:adf:a38c:0:b0:37d:45d0:187 with SMTP id l12csp952565wrb; Fri, 1 Nov 2024 10:09:54 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXmDDjYx2ZHz96OM2t2R84nBVquutZkbQwhuSfEmObRikRE2shbVBqakOjvPjxmivQXC4Q0dQ==@linaro.org X-Google-Smtp-Source: AGHT+IH4Ni0sSt2NmPMJokpmSWMBzoEY2sTc9gy2AAszbze94DeePlUqyRQfWLCJwrzd4X2Z0cTQ X-Received: by 2002:a05:622a:492:b0:460:4ef4:6377 with SMTP id d75a77b69052e-462b8646b74mr64732651cf.6.1730480994531; Fri, 01 Nov 2024 10:09:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1730480994; cv=none; d=google.com; s=arc-20240605; b=Rj692Lw/g2vM22xLCLwpyU5/wXQuVNZDkHcMWicJLe35aGoVGuOYNNz54D06MHRonE rAeqHxEXAokUvjS2j6ozCRBs6joVih4FBSHGqrAAVW/jRR84ncGwlozHKRcZdnQU2N2i H4dIHhU0wEqi0O5SxbRsyZwlWrIxUy21cdtNrKrVVNi4rjPDOCqGgngc74XFmVUb8A0P h+HXQHuJaoGjuJekLIkop9Quw0of88d0BsTzSkLd3HA0R79W1sdZUKBZzW2g3uT8NGgl LSEnJrrPkG/M2op7GaElWdg1tHsTX/aWCgjZp5Y6Iy1FHnNzX4Uu9t57DTatCURZeic6 v05w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature; bh=skjO6/KfjbtXR/JUy1d485PhXpXWJNWAEEtdHsUoy5w=; fh=n6alBGKXWuabqqae4shkz59Y5YoL9NejtiDgdsb6n9w=; b=M1NtHQdN/k1NgVHtuVEfaDY6cRjqVkvm1K0jMoxgiTj/OqXeS/z1cHjAn3Alk6Nxfk EFWKEON+3/KKVy2GBw+q35oQ+TBrVrsgaan0sDKJEpkHcwcKQK17ww/MmmnyrLtRQ4Sg qu1R9XYnXCmQLw4u1XeoNTduN9mSM7Vfg7cTp36C0d/CnFXYfezUtgfXcMQ7jM//wDpl Aq3fs7Q/7if3YuAVFPHUMbLqtV9hgZeuIJPQXSFXqce2lQWX6FOiFqndbI+MZShc029A rSQlsPkRttjJKDy47JRwG0UBFtbCxTzLMG8zzhKYuEuKaBExPkLkC6bTHRxMGB0EpVqw DgfQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I0iOPU4h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-462ad23f839si47057821cf.544.2024.11.01.10.09.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 01 Nov 2024 10:09:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I0iOPU4h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6v8e-0002Gp-AJ; Fri, 01 Nov 2024 13:08:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6v8c-0002GV-HP for qemu-devel@nongnu.org; Fri, 01 Nov 2024 13:08:42 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t6v8b-00064s-0d for qemu-devel@nongnu.org; Fri, 01 Nov 2024 13:08:42 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-71e4e481692so1979739b3a.1 for ; Fri, 01 Nov 2024 10:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1730480919; x=1731085719; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=skjO6/KfjbtXR/JUy1d485PhXpXWJNWAEEtdHsUoy5w=; b=I0iOPU4h1qJxVYLfJhzj+xIcyjTEgCDn8c2rVOXcuPHAcO+owYZlogu7azm0Cb0Oed Rvcuyg7ScCnrMgfrIcIGYRQ9qY3Z6ckxA//tmwl4zDjcGbq4dCr5Lkj+aXq/gkllQleR It2GrF+leRg07qQX/OOvwzgr3dlqNxnrTI2NmMZgtFdphzhKPUM83zC5qn+fh8WFaTdK t8zycXwaNLv8Zqa0hAzzr2T1B/BXzcFdWMj8GU6LHMBLa0OdUtcDMs070tmpR7piQVI7 YAmzGGBvb/VB/6bowHa1W7A/PTuME+BcTBfrrZ6o7pYr+rCZr0xB/+9j0Ug9yT4/V4RA Z9Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730480919; x=1731085719; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=skjO6/KfjbtXR/JUy1d485PhXpXWJNWAEEtdHsUoy5w=; b=BMKvX2ZmQRRAhVBP7R6BA4oIEzQ1RUzJyrlMO6B5w23pKyrN3Qk4nj7mZlSVObHrbW PuESLRH0Qss2RCdtLjqUNpYzOgOW4A2IuOWYdTUyhkeKdghJtoU/nqI54teKs8fcaWKr iKa+uaIoH65VLQ909zOdg40RmN/vCbahgk9q3P/G7lBVv9NZ4TjaUDNVePmZRDmbayg6 x82zMBTtElT2jC/3Hh3UwCWjAEk69XhZRrs3mWTfewmFc9b/6nLez/71SbnbvQCwyFmK R/CNbCu/eYtwirh5ACBYRz9bnoEEI+v7xvGMazjRFYj5oR6ng+8AtA6UrdoneHid6NNR NArQ== X-Gm-Message-State: AOJu0Ywn8EHKOwHzQw12EUEKvfHtGWCmmOM4S1NC5phfRRZ6OmOdCXPB VgTv1mMk4Wq3pF1u4KEDIIpfhNoPPq7zvc0wrLuCunYBLJgl70t74gnIjwXHL9kxdXvzIsDfxFF QuWcdVg== X-Received: by 2002:a05:6a21:1584:b0:1d9:61b:960c with SMTP id adf61e73a8af0-1dba5215963mr6004692637.9.1730480919069; Fri, 01 Nov 2024 10:08:39 -0700 (PDT) Received: from linaro.. (216-180-64-156.dyn.novuscom.net. [216.180.64.156]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-720bc1ceea8sm2865818b3a.42.2024.11.01.10.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 10:08:38 -0700 (PDT) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: Cleber Rosa , qemu-riscv@nongnu.org, Liu Zhiwei , Mahmoud Mandour , Alistair Francis , John Snow , Stefano Garzarella , Thomas Huth , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , "Michael S. Tsirkin" , Weiwei Li , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Konstantin Kostiuk , Pierrick Bouvier , Bin Meng , Paolo Bonzini , Alexandre Iooss , Michael Roth , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P?= =?utf-8?q?=2E_Berrang=C3=A9?= , Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH] hw/riscv: fix build error with clang Date: Fri, 1 Nov 2024 10:08:33 -0700 Message-Id: <20241101170833.1074954-1-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation" ../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64' 187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext) | ^ D:/a/_temp/msys64/clang64/lib/clang/18/include/bmi2intrin.h:217:1: note: previous definition is here 217 | _pext_u64(unsigned long long __X, unsigned long long __Y) | ^ Signed-off-by: Pierrick Bouvier --- hw/riscv/riscv-iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index feb650549ac..f738570bac2 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -184,7 +184,7 @@ static void riscv_iommu_pri(RISCVIOMMUState *s, } /* Portable implementation of pext_u64, bit-mask extraction. */ -static uint64_t _pext_u64(uint64_t val, uint64_t ext) +static uint64_t pext_u64(uint64_t val, uint64_t ext) { uint64_t ret = 0; uint64_t rot = 1; @@ -528,7 +528,7 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUState *s, int cause; /* Interrupt File Number */ - intn = _pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask); + intn = pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask); if (intn >= 256) { /* Interrupt file number out of range */ res = MEMTX_ACCESS_ERROR;