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Tue, 26 Nov 2024 06:01:48 -0800 (PST) Received: from localhost.localdomain ([176.176.143.205]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbedfccsm13310438f8f.101.2024.11.26.06.01.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 26 Nov 2024 06:01:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Jiaxun Yang Subject: [PATCH v3 15/16] target/mips: Convert MIPS16e LI opcodes to decodetree Date: Tue, 26 Nov 2024 15:00:01 +0100 Message-ID: <20241126140003.74871-16-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126140003.74871-1-philmd@linaro.org> References: <20241126140003.74871-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Decode the destination register using the xlat() helper. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/mips16e_16.decode | 8 ++++++++ target/mips/tcg/mips16e_32.decode | 9 +++++++++ target/mips/tcg/mips16e_translate.c | 14 ++++++++++++++ target/mips/tcg/mips16e_translate.c.inc | 11 ----------- 4 files changed, 31 insertions(+), 11 deletions(-) diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode index 82586493f68..bae7bfbb522 100644 --- a/target/mips/tcg/mips16e_16.decode +++ b/target/mips/tcg/mips16e_16.decode @@ -7,3 +7,11 @@ # Reference: MIPS Architecture for Programmers, Volume IV-a # The MIPS16e Application Specific Extension # (Document Number: MD00076) + +&rd_imm rd imm + +%xlat_rx8 8:3 !function=xlat + +@ri ..... ... imm:8 &rd_imm rd=%xlat_rx8 + +LI 01101 ... ........ @ri diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode index fc429049e18..248ee95706d 100644 --- a/target/mips/tcg/mips16e_32.decode +++ b/target/mips/tcg/mips16e_32.decode @@ -7,3 +7,12 @@ # Reference: MIPS Architecture for Programmers, Volume IV-a # The MIPS16e Application Specific Extension # (Document Number: MD00076) + +&rd_imm rd imm !extern + +%immx 0:5 21:6 16:5 +%xlat_rx8 8:3 !function=xlat + +@ri ..... ...... ..... ..... ... ... ..... &rd_imm rd=%xlat_rx8 imm=%immx + +LI 11110 ...... ..... 01101 ... 000 ..... @ri diff --git a/target/mips/tcg/mips16e_translate.c b/target/mips/tcg/mips16e_translate.c index 6de9928b37e..a66f49fe8ed 100644 --- a/target/mips/tcg/mips16e_translate.c +++ b/target/mips/tcg/mips16e_translate.c @@ -9,6 +9,20 @@ #include "qemu/osdep.h" #include "translate.h" +static inline int xlat(DisasContext *ctx, int x) +{ + static const int map[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; + + return map[x]; +} + /* Include the auto-generated decoders. */ #include "decode-mips16e_16.c.inc" #include "decode-mips16e_32.c.inc" + +static bool trans_LI(DisasContext *ctx, arg_rd_imm *a) +{ + gen_li(ctx, a->rd, a->imm); + + return true; +} diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index a57ae4e95b1..f3f09b164ae 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -24,7 +24,6 @@ enum { M16_OPC_SLTI = 0x0a, M16_OPC_SLTIU = 0x0b, M16_OPC_I8 = 0x0c, - M16_OPC_LI = 0x0d, M16_OPC_CMPI = 0x0e, M16_OPC_SD = 0x0f, M16_OPC_LB = 0x10, @@ -582,9 +581,6 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) break; } break; - case M16_OPC_LI: - tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm); - break; case M16_OPC_CMPI: tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm); break; @@ -839,13 +835,6 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) } } break; - case M16_OPC_LI: - { - int16_t imm = (uint8_t) ctx->opcode; - - gen_arith_imm(ctx, OPC_ADDIU, rx, 0, imm); - } - break; case M16_OPC_CMPI: { int16_t imm = (uint8_t) ctx->opcode;