From patchwork Sun Dec 8 22:48:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 848279 Delivered-To: patch@linaro.org Received: by 2002:a5d:50c2:0:b0:385:e875:8a9e with SMTP id f2csp1840000wrt; Sun, 8 Dec 2024 14:50:10 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWVwzi2Ditodq7oK4HTl9NS5inrVO2wgs8d1/It7XMos4xvks6XNAuOuATnhsbP+dVZJCKPRw==@linaro.org X-Google-Smtp-Source: AGHT+IEX6q8rSIj43+6654+lr6e/WAg1nvmmMmdl8XUZew6GUfcWWZ4bUg3gPIXJlV5Jm0N/NSA2 X-Received: by 2002:ac8:5ac5:0:b0:466:a119:f4d3 with SMTP id d75a77b69052e-46734e7127emr183700911cf.45.1733698210097; Sun, 08 Dec 2024 14:50:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733698210; cv=none; d=google.com; s=arc-20240605; b=F4rVnF2lLz8nceGIMKloTjWkyP10M0NbNEPTOphpn1Fm+WjpRQ2RfDwF9rEpUHLUsd mN2BKAv6wbzQ4+pLbgGipjVZx7btuxDM28d/jtuec1yJEjvyGaFRJSZxrY0bh6j2ksC3 kZQE8b6Yosd4mPfXbF7vUxgzr/bTggJGlpRfHhBN3P5YiXH1scfgsVKqwBLiU2k9G2Wi OJp0lsEFLLRlFMKgQ8+B5nh/wFJc3lRKGI5m8nzqvh1FOk4QtthKZDOE2d6uRvqPTooE SF209Km8+hy4xt+Kfph5PcO45JLkr7J7iGVwTmvqtiyUaRQb3o/WfeUrbqwe4u+Ggv76 WMKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=VygN+W9RKPAJjasMCWSLuOlElJZ/pQQzo9TD4o2RJQI=; fh=ZTutxOFfSTK00/NSefao3I8YzT34sqQTgDXNvfsMID8=; b=UFjwAmzCn0DuMA3Nk4w0TnJUmDQYD3jMmsUDcZtRBBBkoLPe7y9+MMXIbjx8u4/8OE O+3Q+qeFvoYBo5kBKSpK7MFqxxcqkm3bJEtKi7nzY0gCDpT5M9dE7t41kOjSSgJRvQN2 RPBggo1R0RK/sFEkPzzobBMMbyYXmw40btiJff6GP7rYU0ZURnzQlf1XGp+FuoQfppGt 6FN0BEqPjptuZCA0b033vkXyZsh6LeyeQs8YdoNirAbKbP0D8RUk5tHhGY14XzsNYEbP ltoOycXQFu1SDUPcljGzm5iujpmGGre9oX/K0AFAIjKt0j3Gs6lrekVgpeD8hCXfLlOZ 0LGg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GDneB3h1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4674e8ddd34si44252841cf.523.2024.12.08.14.50.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 08 Dec 2024 14:50:10 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GDneB3h1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tKQ59-000783-JP; Sun, 08 Dec 2024 17:48:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tKQ57-00077Q-CR for qemu-devel@nongnu.org; Sun, 08 Dec 2024 17:48:53 -0500 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tKQ55-0006CY-HY for qemu-devel@nongnu.org; Sun, 08 Dec 2024 17:48:53 -0500 Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-71de02b24cfso556506a34.1 for ; Sun, 08 Dec 2024 14:48:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733698130; x=1734302930; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VygN+W9RKPAJjasMCWSLuOlElJZ/pQQzo9TD4o2RJQI=; b=GDneB3h1sgCo78LbGrQkFrdUOgWugjuWkaWlwN0nMZPrbBsMeF8HvtRsjwAU7Gv+T+ GauAyfE/Rdq5qd/W8x6M6KKkz4dywNGoSBZ3Ca5dm82x6ox325GCDXu+5Ph13MGtiNpR Rm6DsCTWl6fEBKlE9TBPIBYtCpT8rVQC0CbpMQ5l7gya0Qlp8KhS4PefCVZ3Sfg+Xn4d Xp/GbfACSpOXOBRdC25/RUeESpA8PGCnvvi4lNwFKT0fgemn/9/zIDvmmdtenHbW4Smw 3XJDzi7PPOWiDJIqDYhQ0YnbbGsXCNvvOXwsFg5BRWvzPuF4CfTLy1WzHjtCiwSYqKAJ UBJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733698130; x=1734302930; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VygN+W9RKPAJjasMCWSLuOlElJZ/pQQzo9TD4o2RJQI=; b=dEWbeibAjMTqbV3/knAGywIvL0X2xEpds/nlKD7inkh2Qsj/9tnP4gNjA5jge+FiR0 kSoI4SIJASpMJpZNu2lFT5xBFMYQ55hlKhQ0hV/Cj2t0ynEDWv6/snE8jd/bmyRgDD1u vrKaEI4jJtBhIn1mV5fJbKN3yf8u8k6hWQTLoAfEZe/mS+/FMr2QN0dQBi/0L4qmxE4A 02UAjNYNgsPw3qy4+aoqsFv4qJg1h7lDXw7+FkwshFAztInGjJ6LhdZpUZk70T3NbIZZ O+XDv+ciuy098zjJ305+GE9jtDQVcYlEXg9wkskrk8LuvtcFDFyPn79VYFXdxtO745Z0 Hcbw== X-Gm-Message-State: AOJu0YxHG4ktQCN4hWQbfilG1feu7eCW9x1M2ix3OEuYpuA6cD02sQcx T4KWmxKHcVFXEdIvyNhyP/kUyg8gPCouRL/NbhCOnKBJPLCUr56wgdFIKkrCQjROvSEmIyJrqDj dn/esUQ== X-Gm-Gg: ASbGncuyYqQ/g5ftsOleKEKpOu2FDaLFuGpXPVJTwn8wkHS9x4N+AO6qFqp2Xq4oMDu wNrfW3h1KJxFR4NbzPB1FwkrlUCpvpbxpI8MR1wtXc+DwgFiU/rryPngJoGZiVeab+5UX/b3lT6 BISNpNh2oxJFdSbhwICzVCnLkEDHjvMPCHY2f3x8VY++nUyu9sQxcvX1kdJTjDektLhpVX5Hnp6 ++wiWTQHs7hebs0auPtQJ5IHlr+AOoykvAA+l4kX4tCtHHjfJOJt1D2OoQL6cR19LlVSfETcprp kwhyA7XLhDTkdhCX0y8c4nIzkmMywUJ9pIPQ X-Received: by 2002:a05:6830:700e:b0:71d:4385:665e with SMTP id 46e09a7af769-71dcf4cc128mr6426441a34.9.1733698130362; Sun, 08 Dec 2024 14:48:50 -0800 (PST) Received: from localhost.localdomain (fixed-187-189-51-143.totalplay.net. [187.189.51.143]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71dc497ee8fsm1925198a34.39.2024.12.08.14.48.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Dec 2024 14:48:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: bcain@oss.qualcomm.com, peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk Subject: [PATCH 03/17] target/sparc: Use float*_muladd_scalbn Date: Sun, 8 Dec 2024 16:48:30 -0600 Message-ID: <20241208224844.570491-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241208224844.570491-1-richard.henderson@linaro.org> References: <20241208224844.570491-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use the scalbn interface instead of float_muladd_halve_result. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/sparc/helper.h | 4 +- target/sparc/fop_helper.c | 8 ++-- target/sparc/translate.c | 80 +++++++++++++++++++++++---------------- 3 files changed, 54 insertions(+), 38 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 134e519a37..49ace89858 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -59,7 +59,7 @@ DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_WG, f64, env, f64, f64) -DEF_HELPER_FLAGS_5(fmaddd, TCG_CALL_NO_WG, f64, env, f64, f64, f64, i32) +DEF_HELPER_FLAGS_6(fmaddd, TCG_CALL_NO_WG, f64, env, f64, f64, f64, s32, i32) DEF_HELPER_FLAGS_3(fnaddd, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fnmuld, TCG_CALL_NO_WG, f64, env, f64, f64) @@ -72,7 +72,7 @@ DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_WG, f32, env, f32, f32) -DEF_HELPER_FLAGS_5(fmadds, TCG_CALL_NO_WG, f32, env, f32, f32, f32, i32) +DEF_HELPER_FLAGS_6(fmadds, TCG_CALL_NO_WG, f32, env, f32, f32, f32, s32, i32) DEF_HELPER_FLAGS_3(fnadds, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fnmuls, TCG_CALL_NO_WG, f32, env, f32, f32) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 6f9ccc008a..f4af04f061 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -344,17 +344,17 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) } float32 helper_fmadds(CPUSPARCState *env, float32 s1, - float32 s2, float32 s3, uint32_t op) + float32 s2, float32 s3, int32_t sc, uint32_t op) { - float32 ret = float32_muladd(s1, s2, s3, op, &env->fp_status); + float32 ret = float32_muladd_scalbn(s1, s2, s3, sc, op, &env->fp_status); check_ieee_exceptions(env, GETPC()); return ret; } float64 helper_fmaddd(CPUSPARCState *env, float64 s1, - float64 s2, float64 s3, uint32_t op) + float64 s2, float64 s3, int32_t sc, uint32_t op) { - float64 ret = float64_muladd(s1, s2, s3, op, &env->fp_status); + float64 ret = float64_muladd_scalbn(s1, s2, s3, sc, op, &env->fp_status); check_ieee_exceptions(env, GETPC()); return ret; } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cdd0a95c03..005efb13f1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1364,93 +1364,109 @@ static void gen_op_fabsq(TCGv_i128 dst, TCGv_i128 src) static void gen_op_fmadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3) { - gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(0)); + TCGv_i32 z = tcg_constant_i32(0); + gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, z); } static void gen_op_fmaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3) { - gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(0)); + TCGv_i32 z = tcg_constant_i32(0); + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, z); } static void gen_op_fmsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3) { - int op = float_muladd_negate_c; - gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); + TCGv_i32 z = tcg_constant_i32(0); + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c); + gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, op); } static void gen_op_fmsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3) { - int op = float_muladd_negate_c; - gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); + TCGv_i32 z = tcg_constant_i32(0); + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c); + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, op); } static void gen_op_fnmsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3) { - int op = float_muladd_negate_c | float_muladd_negate_result; - gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); + TCGv_i32 z = tcg_constant_i32(0); + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c | + float_muladd_negate_result); + gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, op); } static void gen_op_fnmsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3) { - int op = float_muladd_negate_c | float_muladd_negate_result; - gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); + TCGv_i32 z = tcg_constant_i32(0); + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c | + float_muladd_negate_result); + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, op); } static void gen_op_fnmadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s3) { - int op = float_muladd_negate_result; - gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); + TCGv_i32 z = tcg_constant_i32(0); + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result); + gen_helper_fmadds(d, tcg_env, s1, s2, s3, z, op); } static void gen_op_fnmaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s3) { - int op = float_muladd_negate_result; - gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); + TCGv_i32 z = tcg_constant_i32(0); + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result); + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, z, op); } /* Use muladd to compute (1 * src1) + src2 / 2 with one rounding. */ static void gen_op_fhadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2) { - TCGv_i32 one = tcg_constant_i32(float32_one); - int op = float_muladd_halve_result; - gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); + TCGv_i32 fone = tcg_constant_i32(float32_one); + TCGv_i32 mone = tcg_constant_i32(-1); + TCGv_i32 op = tcg_constant_i32(0); + gen_helper_fmadds(d, tcg_env, fone, s1, s2, mone, op); } static void gen_op_fhaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2) { - TCGv_i64 one = tcg_constant_i64(float64_one); - int op = float_muladd_halve_result; - gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); + TCGv_i64 fone = tcg_constant_i64(float64_one); + TCGv_i32 mone = tcg_constant_i32(-1); + TCGv_i32 op = tcg_constant_i32(0); + gen_helper_fmaddd(d, tcg_env, fone, s1, s2, mone, op); } /* Use muladd to compute (1 * src1) - src2 / 2 with one rounding. */ static void gen_op_fhsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2) { - TCGv_i32 one = tcg_constant_i32(float32_one); - int op = float_muladd_negate_c | float_muladd_halve_result; - gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); + TCGv_i32 fone = tcg_constant_i32(float32_one); + TCGv_i32 mone = tcg_constant_i32(-1); + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c); + gen_helper_fmadds(d, tcg_env, fone, s1, s2, mone, op); } static void gen_op_fhsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2) { - TCGv_i64 one = tcg_constant_i64(float64_one); - int op = float_muladd_negate_c | float_muladd_halve_result; - gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); + TCGv_i64 fone = tcg_constant_i64(float64_one); + TCGv_i32 mone = tcg_constant_i32(-1); + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_c); + gen_helper_fmaddd(d, tcg_env, fone, s1, s2, mone, op); } /* Use muladd to compute -((1 * src1) + src2 / 2) with one rounding. */ static void gen_op_fnhadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2) { - TCGv_i32 one = tcg_constant_i32(float32_one); - int op = float_muladd_negate_result | float_muladd_halve_result; - gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); + TCGv_i32 fone = tcg_constant_i32(float32_one); + TCGv_i32 mone = tcg_constant_i32(-1); + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result); + gen_helper_fmadds(d, tcg_env, fone, s1, s2, mone, op); } static void gen_op_fnhaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2) { - TCGv_i64 one = tcg_constant_i64(float64_one); - int op = float_muladd_negate_result | float_muladd_halve_result; - gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); + TCGv_i64 fone = tcg_constant_i64(float64_one); + TCGv_i32 mone = tcg_constant_i32(-1); + TCGv_i32 op = tcg_constant_i32(float_muladd_negate_result); + gen_helper_fmaddd(d, tcg_env, fone, s1, s2, mone, op); } static void gen_op_fpexception_im(DisasContext *dc, int ftt)