From patchwork Tue Dec 10 16:17:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 848871 Delivered-To: patch@linaro.org Received: by 2002:adf:ec08:0:b0:385:e875:8a9e with SMTP id x8csp421945wrn; Tue, 10 Dec 2024 08:30:18 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVXcJwKTDAkOl3andtVPpQr9XmTQ6zN0ilcGFAQZGIxmkYgjZooqlCaXAs55VDxdcKvHw/S5g==@linaro.org X-Google-Smtp-Source: AGHT+IEiaVrt5LH4I7pPiXtZdXN7R0yppcaVE5O1DM17DaV9rlb+QAgU22uLr/xUJVx3kkOM+t4U X-Received: by 2002:ac8:59ca:0:b0:458:34fb:5d59 with SMTP id d75a77b69052e-46734cf34admr260542151cf.29.1733848218467; Tue, 10 Dec 2024 08:30:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1733848218; cv=none; d=google.com; s=arc-20240605; b=f7M0neZtVy+zS2PbhA7alpXcw/fyvG+XjpgAkeFV3bx2DyaCl5snBeg84xKsr5bcDx 5MPOk9jejaXMOUAstNhUISrQD1lB9SIrdqj+nBc4bje9LIBVfjSiax6JE+z8xiEwzLIO 68vgrL+8JyYNtjTCjDULSMiq9ijqGc/XPxHwyniycOSHf9F2gUch1IqaUiEf8zd4OIaL 6fz8aB6hyZW2QUz9R0LDUbaKFWUBw+Tz76XokjncfuZzddOLVIbwXX/UUa6MWc9QKqnT zHPGeYMtUuy3069pcmHfePZXwP1qhieMl299uA8v9My4i9w1fs4p/SBMcCcsZ3HYiD8i czZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=c7yOIgCfYAXIlxzBS7Y/cffRsUFfY+7qJLLPOfonFXk=; fh=9Ev+QBUhk6P6vR3LT1wYeDLexozsz44nqjfoyPajZCc=; b=AYBRYxgEm77AaiRzWBoXhUkDwxc5uOQJkN3SmaFQg0AbCY1uCU1YgBwRa813gYIdIO 1EcNrkoSCUnUn4va/QFwa4agitLHppBTjiYhLI5isBtjXHpx2anRS7ujCazGDVvPW2sJ Wdfr31U4u7W7Y76MZCd4VVZLjIdmIt2ZXY6JT4L75QTwQPyUMsLq1SGxya01p2eAHrjP CWMLLm9wg4Wl6qtlf6RFMZtxuLMZQkcbtd6bue70b4sD7ArWwNpkAHJCtTEiLkqRwL0J ql2moLECkDQdtBKMh+FTH9yFUC86JLVbSrL4/yLMsYLILYUW76LNrrHLhmAnCZaXdgev sLig==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=arHEQ+pN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-467296bb290si152836991cf.141.2024.12.10.08.30.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Dec 2024 08:30:18 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=arHEQ+pN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tL32l-0000Xu-BC; Tue, 10 Dec 2024 11:25:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tL32Q-0007uN-F4 for qemu-devel@nongnu.org; Tue, 10 Dec 2024 11:24:44 -0500 Received: from mail-lf1-x134.google.com ([2a00:1450:4864:20::134]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tL32M-0007Xu-RJ for qemu-devel@nongnu.org; Tue, 10 Dec 2024 11:24:42 -0500 Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-53e3a37ae07so3469637e87.3 for ; Tue, 10 Dec 2024 08:24:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733847873; x=1734452673; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c7yOIgCfYAXIlxzBS7Y/cffRsUFfY+7qJLLPOfonFXk=; b=arHEQ+pNMcgYHKTwz+sUdsfCqG8ZE3f8iPRRaKEmkDloURKVliDQbBE+5V7jHVyWYX er4lTNP5cJSYCWZtKGEg0HoPwUGWUOlH8tw23Li+a76l9YWPDLTpPh8wq7t9NZLt4HIt iwTk7InnqkTZozMsiddGYbIQXoOvP9Fleixdbfmy0yG9Bd+hMnq0YSw2ZhbV227KByQy AeB4kLT8tJul6o/OM9HTU5k0lEK9q6PBn2mSvx0GzGsS8wg0HvpehxeVaJb+b7ULv2Qj wLEv7uXhTu00V+23DAc4pYkfuOQ9FNhK00fDDyle/ig2pSyICA7OMf3/5mOJAwMExzW9 pv/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733847873; x=1734452673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c7yOIgCfYAXIlxzBS7Y/cffRsUFfY+7qJLLPOfonFXk=; b=t/inB3x6cjz1bcnRRiSSgUFsEgsxyxpI48BJGZo1kFNopF5y0P9d5SoodNL0t2cwmQ +e/AKyO4Wbw4qUNTc/LbT/Z5GAKwYv0ahxfaoaVB/VXFJs+a2x74gPtH/EinWEk1aXLE nv4QjLyRFek/zjh1palHlpj2sUcuIxztUq1PMpjpJkBR9p/MBSAOCwQAEuJridvC9urB qijp091pxgswzKrDVtQCIZzY7X9J+P5db4e7tYK4KSMf06VGPPUJdz5l6NGYOwDiv2zG 7SYkqNk8mmVTgH+3iPCDZE7mjwfTh6FLjX4CCl/WQxlckIZA0aZlYuLejKfv1ktBmxpW hWdw== X-Gm-Message-State: AOJu0YxGcC/H+mW8/lVh392bgeLi7Y+IvI07VT9hRSmPkFg5wdQpJS4R 4ff9YV17nNRWoD6D59mAbSQylK+zTOZO7N9FTb+TvcvvYjwauY0b2ew6KTSRomqIz5MkMb5tHs9 3V3dsPZJz X-Gm-Gg: ASbGnctz0Mu49PRFwBWlLWxUNXNmriqMokcI+V5DkdtPLyFBBGuf6GzztKo7ySCBZZk 9M12ifYR+92McZGlToQgg18/czJu+a0OYZFNFRH6m7enEymOBZL+T0PxPVHF2Ix0uuCjL/4KArT GQkv3Ej2/AK5C1WjifdrXwzhMfCSwx9EPv93S7FDo+WbkzwWD6S98HMRvWTQQfI4e7+BadqenNk FrBU7DQcpqZc8ABEOoPsovRTKYe4t95Zvn93JhETOfOJY5MvJYQpKKQEYc= X-Received: by 2002:a05:6512:402a:b0:53e:39c2:f02b with SMTP id 2adb3069b0e04-53e39c2f164mr4545331e87.42.1733847873052; Tue, 10 Dec 2024 08:24:33 -0800 (PST) Received: from stoup.. ([91.209.212.80]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5402960b0absm26024e87.102.2024.12.10.08.24.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 08:24:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 57/69] target/arm: Convert FCVT* (vector, integer) scalar to decodetree Date: Tue, 10 Dec 2024 10:17:21 -0600 Message-ID: <20241210161733.1830573-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241210161733.1830573-1-richard.henderson@linaro.org> References: <20241210161733.1830573-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Arm silliness with naming, the scalar insns described as part of the vector instructions, as separate from the "regular" scalar insns which output to general registers. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 133 ++++++++++++++------------------- target/arm/tcg/a64.decode | 30 ++++++++ 2 files changed, 86 insertions(+), 77 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 0f924b07dc..71f1d6f778 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -8674,6 +8674,16 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz, tcg_shift, tcg_fpstatus); tcg_gen_extu_i32_i64(tcg_out, tcg_single); break; + case MO_16 | MO_SIGN: + gen_helper_vfp_toshh(tcg_single, tcg_single, + tcg_shift, tcg_fpstatus); + tcg_gen_extu_i32_i64(tcg_out, tcg_single); + break; + case MO_16: + gen_helper_vfp_touhh(tcg_single, tcg_single, + tcg_shift, tcg_fpstatus); + tcg_gen_extu_i32_i64(tcg_out, tcg_single); + break; default: g_assert_not_reached(); } @@ -8717,6 +8727,42 @@ TRANS(FCVTZU_g, do_fcvt_g, a, FPROUNDING_ZERO, false) TRANS(FCVTAS_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, true) TRANS(FCVTAU_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, false) +/* + * FCVT* (vector), scalar version. + * Which sounds weird, but really just means output to fp register + * instead of output to general register. Input and output element + * size are always equal. + */ +static bool do_fcvt_f(DisasContext *s, arg_fcvt *a, + ARMFPRounding rmode, bool is_signed) +{ + TCGv_i64 tcg_int; + int check = fp_access_check_scalar_hsd(s, a->esz); + + if (check <= 0) { + return check == 0; + } + + tcg_int = tcg_temp_new_i64(); + do_fcvt_scalar(s, a->esz | (is_signed ? MO_SIGN : 0), + a->esz, tcg_int, a->shift, a->rn, rmode); + + clear_vec(s, a->rd); + write_vec_element(s, tcg_int, a->rd, 0, a->esz); + return true; +} + +TRANS(FCVTNS_f, do_fcvt_f, a, FPROUNDING_TIEEVEN, true) +TRANS(FCVTNU_f, do_fcvt_f, a, FPROUNDING_TIEEVEN, false) +TRANS(FCVTPS_f, do_fcvt_f, a, FPROUNDING_POSINF, true) +TRANS(FCVTPU_f, do_fcvt_f, a, FPROUNDING_POSINF, false) +TRANS(FCVTMS_f, do_fcvt_f, a, FPROUNDING_NEGINF, true) +TRANS(FCVTMU_f, do_fcvt_f, a, FPROUNDING_NEGINF, false) +TRANS(FCVTZS_f, do_fcvt_f, a, FPROUNDING_ZERO, true) +TRANS(FCVTZU_f, do_fcvt_f, a, FPROUNDING_ZERO, false) +TRANS(FCVTAS_f, do_fcvt_f, a, FPROUNDING_TIEAWAY, true) +TRANS(FCVTAU_f, do_fcvt_f, a, FPROUNDING_TIEAWAY, false) + static bool trans_FJCVTZS(DisasContext *s, arg_FJCVTZS *a) { if (!dc_isar_feature(aa64_jscvt, s)) { @@ -9776,10 +9822,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) int opcode = extract32(insn, 12, 5); int size = extract32(insn, 22, 2); bool u = extract32(insn, 29, 1); - bool is_fcvt = false; - int rmode; - TCGv_i32 tcg_rmode; - TCGv_ptr tcg_fpstatus; switch (opcode) { case 0xc ... 0xf: @@ -9824,15 +9866,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) case 0x5b: /* FCVTMU */ case 0x7a: /* FCVTPU */ case 0x7b: /* FCVTZU */ - is_fcvt = true; - rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); - break; case 0x1c: /* FCVTAS */ case 0x5c: /* FCVTAU */ - /* TIEAWAY doesn't fit in the usual rounding mode encoding */ - is_fcvt = true; - rmode = FPROUNDING_TIEAWAY; - break; case 0x56: /* FCVTXN, FCVTXN2 */ default: unallocated_encoding(s); @@ -9851,59 +9886,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } - - if (!fp_access_check(s)) { - return; - } - - if (is_fcvt) { - tcg_fpstatus = fpstatus_ptr(FPST_FPCR); - tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus); - } else { - tcg_fpstatus = NULL; - tcg_rmode = NULL; - } - - if (size == 3) { - TCGv_i64 tcg_rn = read_fp_dreg(s, rn); - TCGv_i64 tcg_rd = tcg_temp_new_i64(); - - handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus); - write_fp_dreg(s, rd, tcg_rd); - } else { - TCGv_i32 tcg_rn = tcg_temp_new_i32(); - TCGv_i32 tcg_rd = tcg_temp_new_i32(); - - read_vec_element_i32(s, tcg_rn, rn, 0, size); - - switch (opcode) { - case 0x1a: /* FCVTNS */ - case 0x1b: /* FCVTMS */ - case 0x1c: /* FCVTAS */ - case 0x3a: /* FCVTPS */ - case 0x3b: /* FCVTZS */ - gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0), - tcg_fpstatus); - break; - case 0x5a: /* FCVTNU */ - case 0x5b: /* FCVTMU */ - case 0x5c: /* FCVTAU */ - case 0x7a: /* FCVTPU */ - case 0x7b: /* FCVTZU */ - gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0), - tcg_fpstatus); - break; - default: - case 0x7: /* SQABS, SQNEG */ - g_assert_not_reached(); - } - - write_fp_sreg(s, rd, tcg_rd); - } - - if (is_fcvt) { - gen_restore_rmode(tcg_rmode, tcg_fpstatus); - } + g_assert_not_reached(); } /* AdvSIMD shift by immediate @@ -10391,30 +10374,26 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) TCGv_i32 tcg_res = tcg_temp_new_i32(); switch (fpop) { - case 0x1a: /* FCVTNS */ - case 0x1b: /* FCVTMS */ - case 0x1c: /* FCVTAS */ - case 0x3a: /* FCVTPS */ - case 0x3b: /* FCVTZS */ - gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); - break; case 0x3d: /* FRECPE */ gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); break; case 0x3f: /* FRECPX */ gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); + break; + default: + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ case 0x7a: /* FCVTPU */ case 0x7b: /* FCVTZU */ - gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); - break; - case 0x7d: /* FRSQRTE */ - gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); - break; - default: g_assert_not_reached(); } diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 5e02144f65..f7fcc32adc 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -1652,6 +1652,36 @@ UQXTN_s 0111 1110 ..1 00001 01001 0 ..... ..... @rr_e FCVTXN_s 0111 1110 011 00001 01101 0 ..... ..... @rr_s +@icvt_h . ....... .. ...... ...... rn:5 rd:5 \ + &fcvt sf=0 esz=1 shift=0 +@icvt_sd . ....... .. ...... ...... rn:5 rd:5 \ + &fcvt sf=0 esz=%esz_sd shift=0 + +FCVTNS_f 0101 1110 011 11001 10101 0 ..... ..... @icvt_h +FCVTNS_f 0101 1110 0.1 00001 10101 0 ..... ..... @icvt_sd +FCVTNU_f 0111 1110 011 11001 10101 0 ..... ..... @icvt_h +FCVTNU_f 0111 1110 0.1 00001 10101 0 ..... ..... @icvt_sd + +FCVTPS_f 0101 1110 111 11001 10101 0 ..... ..... @icvt_h +FCVTPS_f 0101 1110 1.1 00001 10101 0 ..... ..... @icvt_sd +FCVTPU_f 0111 1110 111 11001 10101 0 ..... ..... @icvt_h +FCVTPU_f 0111 1110 1.1 00001 10101 0 ..... ..... @icvt_sd + +FCVTMS_f 0101 1110 011 11001 10111 0 ..... ..... @icvt_h +FCVTMS_f 0101 1110 0.1 00001 10111 0 ..... ..... @icvt_sd +FCVTMU_f 0111 1110 011 11001 10111 0 ..... ..... @icvt_h +FCVTMU_f 0111 1110 0.1 00001 10111 0 ..... ..... @icvt_sd + +FCVTZS_f 0101 1110 111 11001 10111 0 ..... ..... @icvt_h +FCVTZS_f 0101 1110 1.1 00001 10111 0 ..... ..... @icvt_sd +FCVTZU_f 0111 1110 111 11001 10111 0 ..... ..... @icvt_h +FCVTZU_f 0111 1110 1.1 00001 10111 0 ..... ..... @icvt_sd + +FCVTAS_f 0101 1110 011 11001 11001 0 ..... ..... @icvt_h +FCVTAS_f 0101 1110 0.1 00001 11001 0 ..... ..... @icvt_sd +FCVTAU_f 0111 1110 011 11001 11001 0 ..... ..... @icvt_h +FCVTAU_f 0111 1110 0.1 00001 11001 0 ..... ..... @icvt_sd + # Advanced SIMD two-register miscellaneous SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e