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[PULL,75/85] MAINTAINERS: correct my email address

Message ID	20241213173229.3308926-76-peter.maydell@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 75/85] MAINTAINERS: correct my email address Date: Fri, 13 Dec 2024 17:32:19 +0000 Message-Id: <20241213173229.3308926-76-peter.maydell@linaro.org> In-Reply-To: <20241213173229.3308926-1-peter.maydell@linaro.org> References: <20241213173229.3308926-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/85] target/arm: Add section labels for "Data Processing (register)" \| expand [PULL,01/85] target/arm: Add section labels for "Data Processing (register)" [PULL,02/85] target/arm: Convert UDIV, SDIV to decodetree [PULL,03/85] target/arm: Convert LSLV, LSRV, ASRV, RORV to decodetree [PULL,04/85] target/arm: Convert CRC32, CRC32C to decodetree [PULL,05/85] target/arm: Convert SUBP, IRG, GMI to decodetree [PULL,06/85] target/arm: Convert PACGA to decodetree [PULL,07/85] target/arm: Convert RBIT, REV16, REV32, REV64 to decodetree [PULL,08/85] target/arm: Convert CLZ, CLS to decodetree [PULL,09/85] target/arm: Convert PAC[ID], AUT[ID] to decodetree [PULL,10/85] target/arm: Convert XPAC[ID] to decodetree [PULL,11/85] target/arm: Convert disas_logic_reg to decodetree [PULL,12/85] target/arm: Convert disas_add_sub_ext_reg to decodetree [PULL,13/85] target/arm: Convert disas_add_sub_reg to decodetree [PULL,14/85] target/arm: Convert disas_data_proc_3src to decodetree [PULL,15/85] target/arm: Convert disas_adc_sbc to decodetree [PULL,16/85] target/arm: Convert RMIF to decodetree [PULL,17/85] target/arm: Convert SETF8, SETF16 to decodetree [PULL,18/85] target/arm: Convert CCMP, CCMN to decodetree [PULL,19/85] target/arm: Convert disas_cond_select to decodetree [PULL,20/85] target/arm: Introduce fp_access_check_scalar_hsd [PULL,21/85] target/arm: Introduce fp_access_check_vector_hsd [PULL,22/85] target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree [PULL,23/85] target/arm: Fix decode of fp16 vector fabs, fneg, fsqrt [PULL,24/85] target/arm: Convert FMOV, FABS, FNEG (scalar) to decodetree [PULL,25/85] target/arm: Pass fpstatus to vfp_sqrt* [PULL,26/85] target/arm: Remove helper_sqrt_f16 [PULL,27/85] target/arm: Convert FSQRT (scalar) to decodetree [PULL,28/85] target/arm: Convert FRINT[NPMSAXI] (scalar) to decodetree [PULL,29/85] target/arm: Convert BFCVT to decodetree [PULL,30/85] target/arm: Convert FRINT{32, 64}[ZX] (scalar) to decodetree [PULL,31/85] target/arm: Convert FCVT (scalar) to decodetree [PULL,32/85] target/arm: Convert handle_fpfpcvt to decodetree [PULL,33/85] target/arm: Convert FJCVTZS to decodetree [PULL,34/85] target/arm: Convert handle_fmov to decodetree [PULL,35/85] target/arm: Convert SQABS, SQNEG to decodetree [PULL,36/85] target/arm: Convert ABS, NEG to decodetree [PULL,37/85] target/arm: Introduce gen_gvec_cls, gen_gvec_clz [PULL,38/85] target/arm: Convert CLS, CLZ (vector) to decodetree [PULL,39/85] target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit [PULL,40/85] target/arm: Convert CNT, NOT, RBIT (vector) to decodetree [PULL,41/85] target/arm: Convert CMGT, CMGE, GMLT, GMLE, CMEQ (zero) to decodetree [PULL,42/85] target/arm: Introduce gen_gvec_rev{16,32,64} [PULL,43/85] target/arm: Convert handle_rev to decodetree [PULL,44/85] target/arm: Move helper_neon_addlp_{s8, s16} to neon_helper.c [PULL,45/85] target/arm: Introduce gen_gvec_{s,u}{add,ada}lp [PULL,46/85] target/arm: Convert handle_2misc_pairwise to decodetree [PULL,47/85] target/arm: Remove helper_neon_{add,sub}l_u{16,32} [PULL,48/85] target/arm: Introduce clear_vec [PULL,49/85] target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetree [PULL,50/85] target/arm: Convert FCVTN, BFCVTN to decodetree [PULL,51/85] target/arm: Convert FCVTXN to decodetree [PULL,52/85] target/arm: Convert SHLL to decodetree [PULL,53/85] target/arm: Implement gen_gvec_fabs, gen_gvec_fneg [PULL,54/85] target/arm: Convert FABS, FNEG (vector) to decodetree [PULL,55/85] target/arm: Convert FSQRT (vector) to decodetree [PULL,56/85] target/arm: Convert FRINT* (vector) to decodetree [PULL,57/85] target/arm: Convert FCVT* (vector, integer) scalar to decodetree [PULL,58/85] target/arm: Convert FCVT* (vector, fixed-point) scalar to decodetree [PULL,59/85] target/arm: Convert [US]CVTF (vector, integer) scalar to decodetree [PULL,60/85] target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree [PULL,61/85] target/arm: Rename helper_gvec_vcvt_[hf][su] with _rz [PULL,62/85] target/arm: Convert [US]CVTF (vector) to decodetree [PULL,63/85] target/arm: Convert FCVTZ[SU] (vector, fixed-point) to decodetree [PULL,64/85] target/arm: Convert FCVT* (vector, integer) to decodetree [PULL,65/85] target/arm: Convert handle_2misc_fcmp_zero to decodetree [PULL,66/85] target/arm: Convert FRECPE, FRECPX, FRSQRTE to decodetree [PULL,67/85] target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte [PULL,68/85] target/arm: Convert URECPE and URSQRTE to decodetree [PULL,69/85] target/arm: Convert FCVTL to decodetree [PULL,70/85] target/arm: Use float_round_to_odd in helper_fcvtx_f64_to_f32 [PULL,71/85] docs/system/arm/orangepi: update links [PULL,72/85] docs/system/arm/fby35: document execute-in-place property [PULL,73/85] docs/system/arm/xlnx-versal-virt: document ospi-flash property [PULL,74/85] docs/system/arm/virt: document missing properties [PULL,75/85] MAINTAINERS: correct my email address [PULL,76/85] target/arm: Move some TLBI insns to their own source file [PULL,77/85] target/arm: Move TLBI insns for AArch32 EL2 to tlbi_insn_helper.c [PULL,78/85] target/arm: Move AArch64 TLBI insns from v8_cp_reginfo[] [PULL,79/85] target/arm: Move the AArch64 EL2 TLBI insns [PULL,80/85] target/arm: Move AArch64 EL3 TLBI insns [PULL,81/85] target/arm: Move TLBI range insns [PULL,82/85] target/arm: Move the TLBI OS insns to tlb-insns.c. [PULL,83/85] target/arm: Move small helper functions to tlb-insns.c [PULL,84/85] target/arm: Move RME TLB insns to tlb-insns.c [PULL,85/85] target/arm: Simplify condition for tlbi_el2_cp_reginfo[]

Commit Message

Peter Maydell Dec. 13, 2024, 5:32 p.m. UTC

From: Brian Cain <brian.cain@oss.qualcomm.com>

Mea culpa, I don't know how I got this wrong in 2dfe93699c.  Still
getting used to the new address, I suppose.  Somehow I got it right in the
mailmap, though.

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Message-id: 20241209181242.1434231-1-brian.cain@oss.qualcomm.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 7c1ab51b2d1..822f34344b0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -226,7 +226,7 @@  F: target/avr/
 F: tests/functional/test_avr_mega2560.py
 
 Hexagon TCG CPUs
-M: Brian Cain <bcain@oss.qualcomm.com>
+M: Brian Cain <brian.cain@oss.qualcomm.com>
 S: Supported
 F: target/hexagon/
 X: target/hexagon/idef-parser/