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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c89e126sm29890799f8f.65.2024.12.30.07.39.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Dec 2024 07:39:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Stafford Horne , Zhao Liu , qemu-ppc@nongnu.org, Yanan Wang , Eduardo Habkost , Song Gao , Bernhard Beschow , qemu-arm@nongnu.org, Marcel Apfelbaum , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 2/3] target/cpus: Remove pointless re-assignment of CPUState::exception_index Date: Mon, 30 Dec 2024 16:39:28 +0100 Message-ID: <20241230153929.87137-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241230153929.87137-1-philmd@linaro.org> References: <20241230153929.87137-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The CPUState::exception_index field is always re-initialized by the parent CPU ResetHold() handler in cpu_common_reset_hold(), no need to have targets manually initializing it. Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/cpu.c | 1 - target/loongarch/cpu.c | 1 - target/openrisc/cpu.c | 1 - 3 files changed, 3 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6e5434a8e99..9b355bfe902 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -203,7 +203,6 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType type) if (scc->parent_phases.hold) { scc->parent_phases.hold(obj, type); } - cs->exception_index = -1; cs->halted = 0; cpu_set_pc(cs, 0xf0000004); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d611a604704..fd062d2e3e1 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -584,7 +584,6 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type) #ifdef CONFIG_TCG restore_fp_status(env); #endif - cs->exception_index = -1; } static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b7bab0d7abf..84aa9448256 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -101,7 +101,6 @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) cpu->env.pc = 0x100; cpu->env.sr = SR_FO | SR_SM; cpu->env.lock_addr = -1; - cs->exception_index = -1; cpu_set_fpcsr(&cpu->env, 0); set_float_detect_tininess(float_tininess_before_rounding,