| Message ID | 20250130182441.40480-4-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore | expand |
On Thu, 30 Jan 2025 at 18:25, Philippe Mathieu-Daudé <philmd@linaro.org> wrote: > > When not specified, Cortex-A9MP configures its GIC with 64 external > IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts > configurable"). Add the GIC_EXT_IRQS definition (with a comment) > to make that explicit. > > Except explicitly setting a property value to its same implicit > value, there is no logical change intended. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > hw/arm/realview.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/realview.c b/hw/arm/realview.c > index 9900a98f3b8..4a62c83506b 100644 > --- a/hw/arm/realview.c > +++ b/hw/arm/realview.c > @@ -35,6 +35,14 @@ > #define SMP_BOOT_ADDR 0xe0000000 > #define SMP_BOOTREG_ADDR 0x10000030 > > +/* > + * The Cortex-A9MP may have anything from 0 to 224 external interrupt > + * IRQ lines (with another 32 internal). We default to 64+32, which > + * is the number provided by the Cortex-A9MP test chip in the > + * Realview PBX-A9 and Versatile Express A9 development boards. > + */ On the other hand, this really *is* the Realview PBX-A9 development board. So we can just say that that's the right number (and the vexpress is irrelevant, and the range of settings the CPU itself can have isn't very important either). (PS: there's no verb "to explicit" in English (ignoring some obscure obsolete ones); French "expliciter" => English "to make explicit"; or you in the case of the subject line here, "specify explicitly" is probably most natural.) > +#define GIC_EXT_IRQS 64 > + > /* Board init. */ > > static struct arm_boot_info realview_binfo = { > @@ -185,7 +193,12 @@ static void realview_init(MachineState *machine, > sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); > > if (is_mpcore) { > - dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); > + if (is_pb) { > + dev = qdev_new(TYPE_A9MPCORE_PRIV); > + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); > + } else { > + dev = qdev_new("realview_mpcore"); > + } > qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); > busdev = SYS_BUS_DEVICE(dev); > sysbus_realize_and_unref(busdev, &error_fatal); > @@ -201,7 +214,7 @@ static void realview_init(MachineState *machine, > /* For now just create the nIRQ GIC, and ignore the others. */ > dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]); > } > - for (n = 0; n < 64; n++) { > + for (n = 0; n < GIC_EXT_IRQS; n++) { > pic[n] = qdev_get_gpio_in(dev, n); > } > > -- > 2.47.1 thanks -- PMM
diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 9900a98f3b8..4a62c83506b 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -35,6 +35,14 @@ #define SMP_BOOT_ADDR 0xe0000000 #define SMP_BOOTREG_ADDR 0x10000030 +/* + * The Cortex-A9MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + */ +#define GIC_EXT_IRQS 64 + /* Board init. */ static struct arm_boot_info realview_binfo = { @@ -185,7 +193,12 @@ static void realview_init(MachineState *machine, sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); if (is_mpcore) { - dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); + if (is_pb) { + dev = qdev_new(TYPE_A9MPCORE_PRIV); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); + } else { + dev = qdev_new("realview_mpcore"); + } qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); @@ -201,7 +214,7 @@ static void realview_init(MachineState *machine, /* For now just create the nIRQ GIC, and ignore the others. */ dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]); } - for (n = 0; n < 64; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); }
When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/arm/realview.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-)