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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d9335b6sm63108675e9.2.2025.02.06.09.32.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 09:32:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bastian Koppelmann , =?utf-8?q?Philippe_?= =?utf-8?q?Mathieu-Daud=C3=A9?= Subject: [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift() Date: Thu, 6 Feb 2025 18:32:58 +0100 Message-ID: <20250206173258.36624-1-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We only support 32-bit TriCore architecture. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bastian Koppelmann --- target/tricore/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 6819b776686..c5b783b6a70 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -5936,7 +5936,7 @@ static void decode_rr_logical_shift(DisasContext *ctx) break; case OPC2_32_RR_CLO: tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); - tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32); break; case OPC2_32_RR_CLO_H: gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); @@ -5948,7 +5948,7 @@ static void decode_rr_logical_shift(DisasContext *ctx) gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); break; case OPC2_32_RR_CLZ: - tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32); break; case OPC2_32_RR_CLZ_H: gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);