From patchwork Mon Feb 10 15:49:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 863786 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e42:0:b0:385:e875:8a9e with SMTP id r2csp1662376wrt; Mon, 10 Feb 2025 07:53:28 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXePifxK/MwWx+FvXXuDnRey20LGz9KGLE5MphO6bK3Taopun9n0ymF/Kbig9xzkpqnYZ8jPQ==@linaro.org X-Google-Smtp-Source: AGHT+IFCrf71ElCol2DpbwsCZeniN7aNfSnLEVA7tBbjANL3URxiPYBFD57vTTHDwUgD70qSaWuC X-Received: by 2002:a05:622a:8e02:b0:471:8c1b:7e33 with SMTP id d75a77b69052e-4718c1b81cbmr47100321cf.33.1739202807874; Mon, 10 Feb 2025 07:53:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739202807; cv=none; d=google.com; s=arc-20240605; b=EJjkS3G0Nj1YqlulSjI6XfQlD27TucKtzI/yrqfZn01t8y0pvtnB4Q4Hpj+Kgnsw0h lRJnQ5pRZeN7DcFaeeYR2bF7KFRXPbpkuPx58KosWt22ot21hYdJGobXOQUgMQjtAD5n lZFU+avZdTZeZLMBiFXgdr7y9bI9zFsygzpw/QRW72j7C/ZzWnRk6ChGYEyyhrEJVW0m w4T6n2rqyIjRcmbHpcxq2vOYoVKo1BWKEol7cXpl63OTe5whF0LLQbRO6C+6F62NJKbs b4ySY4V1JbxxdKtdy501mVBAn3Sl9kDfelwgHdiVmXGrK1YEdqBuCQC5E2e6DiapumAG 2zAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=C5heOUGneotf5f/UOG2KrqgfCQsXkzBU9Lgw0sQAJEA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=I5AU6nLNGXLLeK+hjl0V9oDxi22xa6QI+up5DQDyE0Pfsetz8JGP5s677w+9z2HZzp xmebUvuYlEmsjxe7a/vIhOsW9CdJwCmrzA0QNc1K9SWu+EeDRyjPdVSj0YIb9/WNf7LD 9kjA8Tn3fC43StAXwinZYbMjmV0IvCYXJUOxiTKF3MNwiUNWn4Wr+VwckOSMEyamR2cP qcnaIKVxF9BIQbwY4RARz6xTM4Dhguhu8aW5E316dLZppCqsU7wdGTtASd921TNT9JK+ qClEqOXRhj4yCsaifCcYvSUqNINTHlHHEf8wZDFfhYVDPO29dCbffsRZ6rBclRkscQGP xLRA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a5EvWjUI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-471915b94e5si25911881cf.644.2025.02.10.07.53.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Feb 2025 07:53:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a5EvWjUI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1thW3d-0007wT-0b; Mon, 10 Feb 2025 10:50:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1thW2n-0007Eh-3W for qemu-devel@nongnu.org; Mon, 10 Feb 2025 10:49:57 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1thW2l-0004hu-5R for qemu-devel@nongnu.org; Mon, 10 Feb 2025 10:49:56 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4362f61757fso45148765e9.2 for ; Mon, 10 Feb 2025 07:49:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739202593; x=1739807393; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=C5heOUGneotf5f/UOG2KrqgfCQsXkzBU9Lgw0sQAJEA=; b=a5EvWjUI6yrJ/FeG9V1ub5stDrNBZUbKhKtZzmCxliPUlfhJwIv67Jv6jvh9U1P0Am lll0sKnR/vEGkD21z4s6hbRDNqWSgZV0AfidMI1pvB7n35cKSOev/4wIgmYSg5urA8u1 dLgTAMOYJuTAOFXNlq3vdXPMRmb/15yb4w+DklozddKLPfVXyoXJ+G3CicVpQG+BGrHP BGTdbFedg99dH/0k3RF6uwwItjYrBdOm9zR97Lm6Alr4PK9nf1S+MWf+zs6nT4FPMqCZ 4y9gONnWXj1DBjUG1Ugb68VYA2KFqL4iJou9c/1gh4Z/V5n1LD/hviY7BP9H2ZUnGSad k6tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739202593; x=1739807393; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C5heOUGneotf5f/UOG2KrqgfCQsXkzBU9Lgw0sQAJEA=; b=fCqHjkXo/qdEy0hUW7qhrMl7fcSWlfdXhVVWnt1qfKh15QPKtCDX+6YDopoiR1MeBH VAkDjTHFEBMCZnrB/Sw67KlsmURuc5ZN/qTGFWksujfqIqjmewb87DYRVSC2ZOaeauk6 8eAgnCxHyg97KVpsUGR5/Pu2Wg0k2aSx1EaYaiIRNvDGOW33MTY4oaYYtdVRjYBDU4fD PURF2pqD0cgrhlhgohFcy0c+FXJ5jjcubOImZs7uO6RiyZveA44PlLg7QNBg6e/CT1lf PpIrDx5GC/wsNCpD9GeoXXmXm0c3vaZz+3CURExUJawU48NrumQreTHruf9fbkuJDhaC Mkfg== X-Gm-Message-State: AOJu0Yz0x/UMdiulz3PUgRw/mQFMryMonhhruokWK2LfaIvPeh4Od60n UBZn6R4hqrhdaxvfXPLqym2Q9gIU96ppTTelI++W0e8C/k/RakCeFIl3HPFrbr76M31vVMDczGy + X-Gm-Gg: ASbGncujBpf/SUG1oot4vMEdtgPp/x+XqCyfR7NOXJJy1Tdc2A6K88UFu7bBj4QN7xj ATXp7as+Nq1T2pDjLH/jmomnsc35h7954ciW7URpFBLK2W2rFB5TfHor6GUkJLN4bTS43vmljjY QPz42XP6h5MZXKO0medpXuZuWZkPmPjS8B7cju9GI3IAeX0vWn4Zx1sDGXcTPKVR3bJT6V8BNvE yog2zVvVeDcwGpRqch5nf3ci0HoFMRKn9+IJPI4nSxn2NHD/uK7/IbKfi14N264xDIWXjasQMDo PETbvkke++9RPNRkJ+ZL X-Received: by 2002:a05:600c:1e25:b0:436:17e4:ad4c with SMTP id 5b1f17b1804b1-43924972ce9mr110357145e9.6.1739202592647; Mon, 10 Feb 2025 07:49:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm150612845e9.38.2025.02.10.07.49.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 07:49:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/12] hw/arm/fsl-imx7: Add local 'mpcore/gic' variables Date: Mon, 10 Feb 2025 15:49:37 +0000 Message-Id: <20250210154942.3634878-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210154942.3634878-1-peter.maydell@linaro.org> References: <20250210154942.3634878-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The A7MPCore forward the IRQs from its internal GIC. To make the code clearer, add the 'mpcore' and 'gic' variables. Reviewed-by: Cédric Le Goater Signed-off-by: Philippe Mathieu-Daudé Message-id: 20250130112615.3219-5-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/fsl-imx7.c | 52 +++++++++++++++++++++-------------------------- 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 004bf499376..3374018cde0 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -166,7 +166,8 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) { MachineState *ms = MACHINE(qdev_get_machine()); FslIMX7State *s = FSL_IMX7(dev); - Object *o; + DeviceState *mpcore = DEVICE(&s->a7mpcore); + DeviceState *gic; int i; qemu_irq irq; char name[NAME_SIZE]; @@ -182,7 +183,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) * CPUs */ for (i = 0; i < smp_cpus; i++) { - o = OBJECT(&s->cpu[i]); + Object *o = OBJECT(&s->cpu[i]); /* On uniprocessor, the CBAR is set to 0 */ if (smp_cpus > 1) { @@ -205,16 +206,15 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) /* * A7MPCORE */ - object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", smp_cpus, - &error_abort); - object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", + object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort); + object_property_set_int(OBJECT(mpcore), "num-irq", FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort); + sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX7_A7MPCORE_ADDR); - sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR); - + gic = mpcore; for (i = 0; i < smp_cpus; i++) { - SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); + SysBusDevice *sbd = SYS_BUS_DEVICE(gic); DeviceState *d = DEVICE(qemu_get_cpu(i)); irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); @@ -255,8 +255,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_GPTn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_GPTn_IRQ[i])); } /* @@ -298,12 +297,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) FSL_IMX7_GPIOn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_GPIOn_LOW_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_LOW_IRQ[i])); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_GPIOn_HIGH_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_HIGH_IRQ[i])); } /* @@ -355,8 +352,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, FSL_IMX7_SPIn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_SPIn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_SPIn_IRQ[i])); } /* @@ -381,8 +377,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_I2Cn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_I2Cn_IRQ[i])); } /* @@ -416,7 +411,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]); + irq = qdev_get_gpio_in(gic, FSL_IMX7_UARTn_IRQ[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq); } @@ -454,9 +449,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0)); + irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3)); + irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 3)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq); } @@ -483,7 +478,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, FSL_IMX7_USDHCn_ADDR[i]); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]); + irq = qdev_get_gpio_in(gic, FSL_IMX7_USDHCn_IRQ[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq); } @@ -522,8 +517,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, - qdev_get_gpio_in(DEVICE(&s->a7mpcore), - FSL_IMX7_WDOGn_IRQ[i])); + qdev_get_gpio_in(gic, FSL_IMX7_WDOGn_IRQ[i])); } /* @@ -606,11 +600,11 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_MSI_IRQ); qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ); + irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTA_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ); + irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTB_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ); + irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTC_IRQ); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); @@ -643,7 +637,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, FSL_IMX7_USBn_ADDR[i]); - irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]); + irq = qdev_get_gpio_in(gic, FSL_IMX7_USBn_IRQ[i]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq); snprintf(name, NAME_SIZE, "usbmisc%d", i);