From patchwork Tue Feb 11 16:25:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 864068 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1289:b0:385:e875:8a9e with SMTP id f9csp323591wrx; Tue, 11 Feb 2025 08:27:20 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWVkyA6B7lyLcWFmlo7uSoLKCdw7NSjWpzLgd8ZkyPTlBSwboptE5utkFVe23VfZxWAWcD/CQ==@linaro.org X-Google-Smtp-Source: AGHT+IF44q9XhuRgq+4OPSNK7R2oeZXRsGkq5FDMKZskuDVkWgXNL2c/IgfFzCvdObKqvpLugI9g X-Received: by 2002:a05:620a:4588:b0:7c0:6156:9d48 with SMTP id af79cd13be357-7c06156a12amr1027388885a.31.1739291239933; Tue, 11 Feb 2025 08:27:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739291239; cv=none; d=google.com; s=arc-20240605; b=JrTwINT+0CO27z25VwXN1HH3jtW6AWHyMfZY4zAOiUhQGGa83xLZtmSs3x234RyWDv p1Up5HCk25la64ybeiEyNVp6xaeXvo4fxG93ovg6AXPg70IeJMYtxaPPam5lXX/J+Ku7 9NH3sFzBdcCwR18w32XuATPXNdt0vduGwS9dkxT0g+1STFQnYrq523rfJYyh7IWpFPgQ CTd2se5d9M2dTh+2cJhcigQUj6CpS6J4Z5K07YeUi3jNQucLbB+2JKARClgGPegY7vh6 Fp01f0xG/ADdZG8fGMzTt/zIEf7QW+XqepnA1x6Vo0EDoLzqCfl/VAYP/PpR0F7hFJGw 027A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3EPwG8dd2j64xXzy/tTpfAvYyh9xU2jE/gdTFjY80Pw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=liA9wrK9F8ryqCADOLwq3VwuqkcGYJXnPOGZIAEhp9eKTas4fGz6jAa4MH3nK6LtK2 7h4mHpjwpHk77PAOXURp1iKekeEwrRvJRRU+97+gTrLnn57fkBFpfClEw5IAn2Wll5IR wY/MfrHBIFwlCXATSJqVjMOcDEAhuQVeA634/Ae6/ojvk6Dy5Oq8reBRl4HxIIo/L5K8 zu5QIdVP5sDCxKpM4jovGMbAuy1NPYmpC0DO9Zst9mE10uBT8Ps9XyLGdSzB55g8iMn/ FBZ38/hBedBKVmwPHut3B1EVwU6Oa2Co/ImNnrAXK21Ukbqq34I78qj/G+HaAt7pXlRd CL2Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oIJeKJzQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7c05fd34e10si393589885a.483.2025.02.11.08.27.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 11 Feb 2025 08:27:19 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oIJeKJzQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tht5j-0006Wq-4z; Tue, 11 Feb 2025 11:26:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tht5T-0006Rb-I1 for qemu-devel@nongnu.org; Tue, 11 Feb 2025 11:26:15 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tht5R-00035l-Fk for qemu-devel@nongnu.org; Tue, 11 Feb 2025 11:26:15 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-38dd14c99d3so3213889f8f.3 for ; Tue, 11 Feb 2025 08:26:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739291172; x=1739895972; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3EPwG8dd2j64xXzy/tTpfAvYyh9xU2jE/gdTFjY80Pw=; b=oIJeKJzQloVGhbFMWUv5JyXBvSWf1gG9sCKZZzSunOGO47qCJnQ5zkKyQBmU+FHFCu NeIIxNDpxQ7Zn8Fr+7+NpNuKsN25R6pxfk0LKaskQFEoAJx87PhScA2lulYY6ZQbBdnl TwXU4cuiEwgdza3NHrgykHjSnkMUcU/YZGsTIJXp/ODV1hrYkPvVU32MchX5F2F17W4x HeNYzR1CCCZ85c5fYTxB9OZA3bn1jStf41DCthRXGuraWrAXaCuvYAG7FYhZbyhZ7WIq nd3NUjVnOjlqCe1OAKpRnU4Jv9vUG8PC+2NKVH/qjeyoU5IAC9qLpI9c/jkKBvbDVJNb msHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739291172; x=1739895972; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3EPwG8dd2j64xXzy/tTpfAvYyh9xU2jE/gdTFjY80Pw=; b=gRoV5Q5+yK3QpcA4wKu/TLG/7qz2VjmfzN77FyeQ+yEYIWjiWqUOtnFgCB06eWpUSS UgFI7u/NT9ewSqqfiR8hvAY1VFB8sNFxG/+iDr9Zi8Qqd33FKK7K6yaGpEdCVE8kSCSs yqsvzGsS66NIu2HWKOdif8uQLZQA/9T6oca8zvzPb2rFOMpsIjpX2ZMe0ffBWTtmI+LE 68xoDbhMVKBZ5OzjNWnzuu5MYJK4vUbpMMs2BmlaUBP2e+gPjRJS4ZYBL7q5TFvt4Vgw 0FXGS9L8x90o4HJ0x6WDTUdTTce+HrEtsYaGzejojvYsHICHnZOvraeIaGbFIirZHLEY YEHA== X-Gm-Message-State: AOJu0YwZ0IezT7mawvL5/rnNJ5Pvn0tF9/m+QFqApnns/oD9OOUtUJjp ljxWl8R3jVcRGYPMHxGHz//oHU3uPSI9ZxPI4S1FBSV1Jprl2tViP2BHed7kJwgBEXKORktksB8 1 X-Gm-Gg: ASbGncsSFwDVswQ6A74ZY/9U9uzpXk+m4g3EXkn9UAnhay8U5FHCz/Mm/jhTQ141P5M sw2vLswVTG2Rb7CpCctM7uo1tZGeO4wAPnHVs0laAxtuxFiPOH7+5HyZKvqRCgl8VwrR3Na5fbM l36xYdONAwESzsW7KWi2JqWo8/v3xdK/OcrwCbAMBq7KXKetlKW+SIBozs7KDihcp08spdgXrXu cPqEi+QVYjtrGY2eJPhuh7xC4Jmlw1Wcl96Pfmssq8R+W5Rs0ZKnk+t071qy8SsTAWLk6noyPbe daDYkM4uq6F1IAGHUVCa X-Received: by 2002:a5d:6d83:0:b0:38d:e1ab:d785 with SMTP id ffacd0b85a97d-38de1abda3fmr7274669f8f.14.1739291171952; Tue, 11 Feb 2025 08:26:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4393f202721sm82660455e9.21.2025.02.11.08.26.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2025 08:26:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/68] target/arm: Add FPCR.NEP to TBFLAGS Date: Tue, 11 Feb 2025 16:25:00 +0000 Message-Id: <20250211162554.4135349-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211162554.4135349-1-peter.maydell@linaro.org> References: <20250211162554.4135349-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For FEAT_AFP, we want to emit different code when FPCR.NEP is set, so that instead of zeroing the high elements of a vector register when we write the output of a scalar operation to it, we instead merge in those elements from one of the source registers. Since this affects the generated code, we need to put FPCR.NEP into the TBFLAGS. FPCR.NEP is treated as 0 when in streaming SVE mode and FEAT_SME_FA64 is not implemented or not enabled; we can implement this logic in rebuild_hflags_a64(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/tcg/translate.h | 2 ++ target/arm/tcg/hflags.c | 9 +++++++++ target/arm/tcg/translate-a64.c | 1 + 4 files changed, 13 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 51fc50980b3..24b0a5fcb9f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3214,6 +3214,7 @@ FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) /* Set if FEAT_NV2 RAM accesses are big-endian */ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */ +FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */ /* * Helpers for using the above. Note that only the A64 accessors use diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 3be3fcbe728..0dff00015e8 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -157,6 +157,8 @@ typedef struct DisasContext { bool nv2_mem_be; /* True if FPCR.AH is 1 (alternate floating point handling) */ bool fpcr_ah; + /* True if FPCR.NEP is 1 (FEAT_AFP scalar upper-element result handling) */ + bool fpcr_nep; /* * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index b3a78564ec1..9e6a1869f94 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -407,6 +407,15 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, if (env->vfp.fpcr & FPCR_AH) { DP_TBFLAG_A64(flags, AH, 1); } + if (env->vfp.fpcr & FPCR_NEP) { + /* + * In streaming-SVE without FA64, NEP behaves as if zero; + * compare pseudocode IsMerging() + */ + if (!(EX_TBFLAG_A64(flags, PSTATE_SM) && !sme_fa64(env, el))) { + DP_TBFLAG_A64(flags, NEP, 1); + } + } return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f9b62a2c4fd..d94a0022e4c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -9742,6 +9742,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->nv2_mem_e20 = EX_TBFLAG_A64(tb_flags, NV2_MEM_E20); dc->nv2_mem_be = EX_TBFLAG_A64(tb_flags, NV2_MEM_BE); dc->fpcr_ah = EX_TBFLAG_A64(tb_flags, AH); + dc->fpcr_nep = EX_TBFLAG_A64(tb_flags, NEP); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs;