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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f22fe1dffsm328860f8f.98.2025.02.12.07.44.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 12 Feb 2025 07:44:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , Peter Maydell , Rob Herring , Igor Mitsyanko , qemu-arm@nongnu.org, =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 6/8] hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs Date: Wed, 12 Feb 2025 16:43:31 +0100 Message-ID: <20250212154333.28644-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250212154333.28644-1-philmd@linaro.org> References: <20250212154333.28644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When not specified, Cortex-A9MP configures its GIC with 64 external IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"), and Cortex-15MP to 128 (see commit 528622421eb "hw/cpu/a15mpcore: Correct default value for num-irq"). The Versatile Express board however expects a fixed set of 64 interrupts (see the fixed IRQ length when this board was added in commit 2055283bcc8 ("hw/vexpress: Add model of ARM Versatile Express board"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly setting a property value to its same implicit value, there is no logical change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/vexpress.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index b886d16c023..9676fc770fb 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -51,6 +51,8 @@ #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) +#define GIC_EXT_IRQS 64 /* Versatile Express A9 development board */ + /* Number of virtio transports to create (0..8; limited by * number of available IRQ lines). */ @@ -241,6 +243,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type, */ dev = qdev_new(privdev); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, periphbase); @@ -251,7 +254,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type, * external interrupts starting from 32 (because there * are internal interrupts 0..31). */ - for (n = 0; n < 64; n++) { + for (n = 0; n < GIC_EXT_IRQS; n++) { pic[n] = qdev_get_gpio_in(dev, n); } @@ -543,7 +546,7 @@ static void vexpress_common_init(MachineState *machine) VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); VEDBoardInfo *daughterboard = vmc->daughterboard; DeviceState *dev, *sysctl, *pl041; - qemu_irq pic[64]; + qemu_irq pic[GIC_EXT_IRQS]; uint32_t sys_id; DriveInfo *dinfo; PFlashCFI01 *pflash0;