diff mbox series

[1/9] target/microblaze: Split out mb_unaligned_access_internal

Message ID 20250212220155.1147144-2-richard.henderson@linaro.org
State New
Headers show
Series target/microblaze: Always use TARGET_LONG_BITS == 32 | expand

Commit Message

Richard Henderson Feb. 12, 2025, 10:01 p.m. UTC 
Use an explicit 64-bit type for the address to store in EAR.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/cpu.h    |  3 +++
 target/microblaze/helper.c | 25 ++++++++++++++++---------
 2 files changed, 19 insertions(+), 9 deletions(-)
diff mbox series

Patch

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index f6879eee35..45f7f49809 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -372,6 +372,9 @@  bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
 hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
                                         MemTxAttrs *attrs);
 #endif /* !CONFIG_USER_ONLY */
+G_NORETURN void mb_unaligned_access_internal(CPUState *cs, uint64_t addr,
+                                             MMUAccessType access_type,
+                                             uintptr_t retaddr);
 G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
                                            MMUAccessType access_type,
                                            int mmu_idx, uintptr_t retaddr);
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 5d3259ce31..8b096e3e58 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -268,20 +268,20 @@  bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 
 #endif /* !CONFIG_USER_ONLY */
 
-void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
-                                MMUAccessType access_type,
-                                int mmu_idx, uintptr_t retaddr)
+G_NORETURN
+void mb_unaligned_access_internal(CPUState *cs, uint64_t addr,
+                                  MMUAccessType access_type, uintptr_t retaddr)
 {
-    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+    CPUMBState *env = cpu_env(cs);
     uint32_t esr, iflags;
 
     /* Recover the pc and iflags from the corresponding insn_start.  */
     cpu_restore_state(cs, retaddr);
-    iflags = cpu->env.iflags;
+    iflags = env->iflags;
 
     qemu_log_mask(CPU_LOG_INT,
-                  "Unaligned access addr=" TARGET_FMT_lx " pc=%x iflags=%x\n",
-                  (target_ulong)addr, cpu->env.pc, iflags);
+                  "Unaligned access addr=0x%" PRIx64 " pc=%x iflags=%x\n",
+                  addr, env->pc, iflags);
 
     esr = ESR_EC_UNALIGNED_DATA;
     if (likely(iflags & ESR_ESS_FLAG)) {
@@ -290,8 +290,15 @@  void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
         qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n");
     }
 
-    cpu->env.ear = addr;
-    cpu->env.esr = esr;
+    env->ear = addr;
+    env->esr = esr;
     cs->exception_index = EXCP_HW_EXCP;
     cpu_loop_exit(cs);
 }
+
+void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+                                MMUAccessType access_type,
+                                int mmu_idx, uintptr_t retaddr)
+{
+    mb_unaligned_access_internal(cs, addr, access_type, retaddr);
+}