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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fbf98b4c52sm1964837a91.4.2025.02.12.14.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 14:01:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 1/9] target/microblaze: Split out mb_unaligned_access_internal Date: Wed, 12 Feb 2025 14:01:47 -0800 Message-ID: <20250212220155.1147144-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250212220155.1147144-1-richard.henderson@linaro.org> References: <20250212220155.1147144-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use an explicit 64-bit type for the address to store in EAR. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 3 +++ target/microblaze/helper.c | 25 ++++++++++++++++--------- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f6879eee35..45f7f49809 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -372,6 +372,9 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); #endif /* !CONFIG_USER_ONLY */ +G_NORETURN void mb_unaligned_access_internal(CPUState *cs, uint64_t addr, + MMUAccessType access_type, + uintptr_t retaddr); G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5d3259ce31..8b096e3e58 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -268,20 +268,20 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #endif /* !CONFIG_USER_ONLY */ -void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +G_NORETURN +void mb_unaligned_access_internal(CPUState *cs, uint64_t addr, + MMUAccessType access_type, uintptr_t retaddr) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = cpu_env(cs); uint32_t esr, iflags; /* Recover the pc and iflags from the corresponding insn_start. */ cpu_restore_state(cs, retaddr); - iflags = cpu->env.iflags; + iflags = env->iflags; qemu_log_mask(CPU_LOG_INT, - "Unaligned access addr=" TARGET_FMT_lx " pc=%x iflags=%x\n", - (target_ulong)addr, cpu->env.pc, iflags); + "Unaligned access addr=0x%" PRIx64 " pc=%x iflags=%x\n", + addr, env->pc, iflags); esr = ESR_EC_UNALIGNED_DATA; if (likely(iflags & ESR_ESS_FLAG)) { @@ -290,8 +290,15 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n"); } - cpu->env.ear = addr; - cpu->env.esr = esr; + env->ear = addr; + env->esr = esr; cs->exception_index = EXCP_HW_EXCP; cpu_loop_exit(cs); } + +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + mb_unaligned_access_internal(cs, addr, access_type, retaddr); +}