From patchwork Sun Feb 16 23:10:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 865841 Delivered-To: patch@linaro.org Received: by 2002:a5d:64e6:0:b0:38f:210b:807b with SMTP id g6csp861571wri; Sun, 16 Feb 2025 15:26:58 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWvevZDrr/MqR3QFGAWBeFheFLoF3NnoiL6jj9Q3K1xFh5Du1aZ/9K0doE/PlNF4h3YgLwpkw==@linaro.org X-Google-Smtp-Source: AGHT+IFikze/rJa+rbSPobXYvD4XagSmaXMFm4e4SIlKM6KP+MguPpKwxcjPjWGBnSV3KM+DiNUU X-Received: by 2002:a05:6214:29cb:b0:6df:9771:978e with SMTP id 6a1803df08f44-6e66cd063b0mr127054096d6.34.1739748418000; Sun, 16 Feb 2025 15:26:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1739748417; cv=none; d=google.com; s=arc-20240605; b=fc7LIgR8WwdoTuCuyauAykcyhn/DuYXL4KQG1OdDx1IRUH84m3Z+A8NKw++Mobv5YF lAoXiA4LU3KxkU4uMcrFCR136yfd4Ual45h3JmaBbN2FhHEYyIVhvvShn8uZ7MZbh2Af ezejaA06xAKaNJvYxzEa0dGPcCI9CK6i0zA/eBIzWTKFfyoxGW8dDY84NAlLhN+gwqCW h2GZaLqUs9L1nHj+lcEewUtT67QxIBiCRzOTtN6nCKP3yx9Yr9Mc+DGTq/9LxvOFUymx rqZUDCu2pDraBkk1kEF+HuKdjh5vny+orb7grzXTKa7IeLs4bWKukHyWMlMjt7Qjpexx fwug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iZD6i0yX9mYoq/l1Qlw8Cml8zkcNSR9plgtvagLXob8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=UzCFC9PIs4SsovR6ue8q450g6TtXP46CjrHoCSp5lCPh/oiGATrvzqJ8MoHBzFW/9c E4GgNm1zHXuHeNHM7qiXQXuutRB2aLMhPKbgNjBDnpDTXdCuVRwEmvN+iBsS8VSECCfr LqfyrJHHUeOg4juQKg4kEPHM3MjuC/Wp37IZuCSZhgn2GEVCjNlQ87bg5VScQKusTQib eY4x9SCLLWJGdF6nsVXChWtzrCHt0QI8rTj7PlIo6bglrHsTjuOy35f+UKzC9X4KnWT4 3RxDXaxJcRiqhRMpHN2moo48oVcPuqW9YW5m99Nuexd10PbuJXPHmWLw4vJqNaRxOUHj IoMg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rqjf4Iuu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 6a1803df08f44-6e65d9cc243si79480606d6.432.2025.02.16.15.26.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 16 Feb 2025 15:26:57 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rqjf4Iuu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tjnzv-00059u-0x; Sun, 16 Feb 2025 18:24:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tjnzs-0004zP-Da for qemu-devel@nongnu.org; Sun, 16 Feb 2025 18:24:24 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tjnzp-0006eE-HS for qemu-devel@nongnu.org; Sun, 16 Feb 2025 18:24:24 -0500 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-220e989edb6so68707615ad.1 for ; Sun, 16 Feb 2025 15:24:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1739748259; x=1740353059; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=iZD6i0yX9mYoq/l1Qlw8Cml8zkcNSR9plgtvagLXob8=; b=Rqjf4IuueROtjcneEXlk+UWW1R5I7QbbZXIWJWxDK/S4ZX/dy7jI26ZXHWwUfNBAxG TZARd3NpaeqFBzqF8mbz/9NSxOrmM8XrUMxf3XfvyzAxCiQqgZbVASJwtVrqoMZcKUVW BuUmtNMHItmVFK3ZBAPcxukiPXuMx76WBJ0F+rVI/M1QTJukHZlQdMnZhfQhulxKcA+/ GAp4LxuI0k2G0IawuxHo1GNMkoBTwAbb4M38kRt0pmayGiQs1xa/U01WPwYr5WG2vEl+ AUiW3CGp5GzRsWiBmkDrm/WigBBYLKQpLQF9gMftKWfMWyYRSeit5zC331wWhu2hox8O Oh+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739748259; x=1740353059; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iZD6i0yX9mYoq/l1Qlw8Cml8zkcNSR9plgtvagLXob8=; b=AxJ3pOTMIEp0H+yRmBOUz/WWgIuDyRNWNb7/1Ou05oYDMKgbilumId4W+8sGgGTgY1 DxN8W6UM38IAzFGdYYcG1CvhXnS0avz+dxCP0O7/817nmMUU2jZdGSWS83hG0ur9NNnY rNWEO62ghoNbjpWngF/aRMPk8A/+mH7zpLWNQqXyPeZqF7ZOdebfstyAA5XLT3V2bWAg Wmt4DC7kArxRGONN7ojhuMKu5dIrU8cXt1rTgErN1egFZ2GUosQeKTn8s97Ak5VElRHp 3E7zhiqTu5p7XBNrqy2sudDYZQGixrFD+VwftZgDkQ+Xs0XLASHUXYt+x81wAjzY5lsv yGuw== X-Gm-Message-State: AOJu0YzBmyBAS+2riDbwp2S8iAa07SwbpxM/dnsQNaaBwZLyJzt+RiGa 1hjQqCGZ1yYGMf8ncMlD2RBzr810nom5L+PCC01+iyPd28oXLa+fpttaNnNKReIhlcqq4AB+ucK c X-Gm-Gg: ASbGnctYLzGrX2HG5dp7uc5YCmIbNlnU6QQ3vj+iGvv954bNVJEBefl8P2QUUZw1y8v R7UcsvQCdWTqe9+/1vZqTWQyW/TrdTCGYU0gpN2TColKfQoTA3Xl0VeJ+J4wBvhucK13d/y/PC0 9bCF5ms+xKhOa4YYNXqKteZr8ssVKHsKuBQjTqeIT2jhfOW29Az8Xf5xoqoRywkyf8Bq4fAyMt4 65p9F1Vh8qaiGWKISjIVlP7RbLmTU/rcv7/+5RfN8F8t4DLZUrOei3CcR7WxMtcNEG0PTATAcXc XakLIaXd1eiE3qZkISH7uXai+vx9YHbS924x6JAnUqHE/gs= X-Received: by 2002:a05:6a20:3944:b0:1ee:60fd:bcfa with SMTP id adf61e73a8af0-1ee8cc4b616mr16504867637.35.1739748259566; Sun, 16 Feb 2025 15:24:19 -0800 (PST) Received: from stoup.. (71-212-39-66.tukw.qwest.net. [71.212.39.66]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-adc9ff10056sm4640529a12.72.2025.02.16.15.24.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Feb 2025 15:24:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 162/162] tcg: Remove tcg_out_op Date: Sun, 16 Feb 2025 15:10:11 -0800 Message-ID: <20250216231012.2808572-163-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250216231012.2808572-1-richard.henderson@linaro.org> References: <20250216231012.2808572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All integer opcodes are now converted to TCGOutOp. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/tcg.c | 12 +++--------- tcg/aarch64/tcg-target.c.inc | 7 ------- tcg/arm/tcg-target.c.inc | 7 ------- tcg/i386/tcg-target.c.inc | 7 ------- tcg/loongarch64/tcg-target.c.inc | 7 ------- tcg/mips/tcg-target.c.inc | 7 ------- tcg/ppc/tcg-target.c.inc | 7 ------- tcg/riscv/tcg-target.c.inc | 7 ------- tcg/s390x/tcg-target.c.inc | 7 ------- tcg/sparc64/tcg-target.c.inc | 7 ------- tcg/tci/tcg-target.c.inc | 7 ------- 11 files changed, 3 insertions(+), 79 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 8c2c61f7fa..89859c3713 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -138,9 +138,6 @@ static void tcg_out_mb(TCGContext *s, unsigned bar); static void tcg_out_br(TCGContext *s, TCGLabel *l); static void tcg_out_set_carry(TCGContext *s); static void tcg_out_set_borrow(TCGContext *s); -static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]); #if TCG_TARGET_MAYBE_vec static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src); @@ -5884,12 +5881,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) break; default: - if (def->flags & TCG_OPF_VECTOR) { - tcg_out_vec_op(s, op->opc, type - TCG_TYPE_V64, - TCGOP_VECE(op), new_args, const_args); - } else { - tcg_out_op(s, op->opc, type, new_args, const_args); - } + tcg_debug_assert(def->flags & TCG_OPF_VECTOR); + tcg_out_vec_op(s, op->opc, type - TCG_TYPE_V64, + TCGOP_VECE(op), new_args, const_args); break; } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index be1ca74bc4..e56dc135b6 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2897,13 +2897,6 @@ static const TCGOutOpStore outop_st = { .out_r = tcg_out_st, }; -static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - g_assert_not_reached(); -} - static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg args[TCG_MAX_OP_ARGS], diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 55eef16743..52f1520098 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2646,13 +2646,6 @@ static const TCGOutOpStore outop_st = { .out_r = tcg_out_st, }; -static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - g_assert_not_reached(); -} - static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index ea5c96cbde..fe21ec2634 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3602,13 +3602,6 @@ static const TCGOutOpStore outop_st = { .out_i = tgen_st_i, }; -static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - g_assert_not_reached(); -} - static int const umin_insn[4] = { OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_VPMINUQ }; diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 49522dcd72..b5d00876cb 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -2030,13 +2030,6 @@ static const TCGOutOpStore outop_st = { .out_r = tcg_out_st, }; -static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - g_assert_not_reached(); -} - static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg rd, TCGReg rs) { diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index e5e1b98d13..b3647cc5ad 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2450,13 +2450,6 @@ static const TCGOutOpStore outop_st = { }; -static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - g_assert_not_reached(); -} - static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 824cced94a..2e94778104 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3828,13 +3828,6 @@ static const TCGOutOpStore outop_st = { }; -static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - g_assert_not_reached(); -} - int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index eca1283742..f9417d15f7 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -2642,13 +2642,6 @@ static const TCGOutOpStore outop_st = { }; -static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - g_assert_not_reached(); -} - static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg args[TCG_MAX_OP_ARGS], diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 123e74290a..c0dd9636d9 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -3160,13 +3160,6 @@ static const TCGOutOpStore outop_st = { }; -static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - g_assert_not_reached(); -} - static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 49a4f4f281..09380799e9 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -2069,13 +2069,6 @@ static const TCGOutOpStore outop_st = { }; -static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - g_assert_not_reached(); -} - static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) { diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 50e205211d..35c66a4836 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -1235,13 +1235,6 @@ static const TCGOutOpQemuLdSt2 outop_qemu_st2 = { TCG_TARGET_REG_BITS == 64 ? NULL : tgen_qemu_st2, }; -static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -{ - g_assert_not_reached(); -} - static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg base, intptr_t offset) {