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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e47b6ceesm21094089f8f.45.2025.03.05.07.40.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Mar 2025 07:40:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Paolo Bonzini , Richard Henderson , Pierrick Bouvier , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [RFC PATCH 12/18] hw/mips/mipssim: Use legacy_binary_is_big_endian() Date: Wed, 5 Mar 2025 16:39:22 +0100 Message-ID: <20250305153929.43687-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250305153929.43687-1-philmd@linaro.org> References: <20250305153929.43687-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For legacy binaries, legacy_binary_is_big_endian() is equivalent of the compile time TARGET_BIG_ENDIAN definition. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/mipssim.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index f94dbdc428b..c0959a9e24f 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -47,12 +47,6 @@ #define BIOS_SIZE (4 * MiB) -#if TARGET_BIG_ENDIAN -#define BIOS_FILENAME "mips_bios.bin" -#else -#define BIOS_FILENAME "mipsel_bios.bin" -#endif - static struct _loaderparams { int ram_size; const char *kernel_filename; @@ -65,7 +59,7 @@ typedef struct ResetData { uint64_t vector; } ResetData; -static uint64_t load_kernel(void) +static uint64_t load_kernel(bool is_big_endian) { uint64_t entry, kernel_high, initrd_size; long kernel_size; @@ -75,7 +69,7 @@ static uint64_t load_kernel(void) cpu_mips_kseg0_to_phys, NULL, &entry, NULL, &kernel_high, NULL, - TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB, + is_big_endian ? ELFDATA2MSB : ELFDATA2LSB, EM_MIPS, 1, 0); if (kernel_size < 0) { error_report("could not load kernel '%s': %s", @@ -153,14 +147,16 @@ mips_mipssim_init(MachineState *machine) CPUMIPSState *env; ResetData *reset_info; int bios_size; + bool is_big_endian = legacy_binary_is_big_endian(); + const char *default_bios_filename = is_big_endian ? "mips_bios.bin" + : "mipsel_bios.bin"; unsigned clock_hz = (legacy_binary_is_64bit() ? 6 : 12) * 1000 * 1000; cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); clock_set_hz(cpuclk, clock_hz); /* Init CPUs. */ - cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, - TARGET_BIG_ENDIAN); + cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, is_big_endian); env = &cpu->env; reset_info = g_new0(ResetData, 1); @@ -177,7 +173,8 @@ mips_mipssim_init(MachineState *machine) /* Map the BIOS / boot exception handler. */ memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios); /* Load a BIOS / boot exception handler image. */ - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME); + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware + ?: default_bios_filename); if (filename) { bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE); g_free(filename); @@ -199,7 +196,7 @@ mips_mipssim_init(MachineState *machine) loaderparams.kernel_filename = kernel_filename; loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.initrd_filename = initrd_filename; - reset_info->vector = load_kernel(); + reset_info->vector = load_kernel(is_big_endian); } /* Init CPU internal devices. */