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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd42c6203sm21718385e9.24.2025.03.05.08.13.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Mar 2025 08:13:03 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= , Peter Maydell , Pierrick Bouvier , qemu-arm@nongnu.org, Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [RFC PATCH 3/4] hw/arm/aspeed: Replace TARGET_AARCH64 by legacy_binary_is_64bit() Date: Wed, 5 Mar 2025 17:12:47 +0100 Message-ID: <20250305161248.54901-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250305161248.54901-1-philmd@linaro.org> References: <20250305161248.54901-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For legacy ARM binaries, legacy_binary_is_64bit() is equivalent of the compile time TARGET_AARCH64 definition. Use it as TypeInfo::registerable() callback to dynamically add Aarch64 specific types in qemu-system-aarch64 binary, removing the need of TARGET_AARCH64 #ifdef'ry. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/aspeed.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 98bf071139b..3f18a4501e0 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -28,6 +28,7 @@ #include "hw/loader.h" #include "qemu/error-report.h" #include "qemu/units.h" +#include "qemu/legacy_binary_info.h" #include "hw/qdev-clock.h" #include "system/system.h" @@ -179,11 +180,9 @@ struct AspeedMachineState { #define AST2600_EVB_HW_STRAP1 0x000000C0 #define AST2600_EVB_HW_STRAP2 0x00000003 -#ifdef TARGET_AARCH64 /* AST2700 evb hardware value */ #define AST2700_EVB_HW_STRAP1 0x000000C0 #define AST2700_EVB_HW_STRAP2 0x00000003 -#endif /* Rainier hardware value: (QEMU prototype) */ #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) @@ -1661,7 +1660,6 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } -#ifdef TARGET_AARCH64 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = bmc->soc; @@ -1690,7 +1688,6 @@ static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); } -#endif static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, void *data) @@ -1813,12 +1810,11 @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("ast1030-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, -#ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("ast2700-evb"), .parent = TYPE_ASPEED_MACHINE, + .registerable = legacy_binary_is_64bit, .class_init = aspeed_machine_ast2700_evb_class_init, -#endif }, { .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE,