From patchwork Fri Mar 7 18:56:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 871247 Delivered-To: patch@linaro.org Received: by 2002:a5d:64c8:0:b0:38f:210b:807b with SMTP id f8csp916212wri; Fri, 7 Mar 2025 10:59:45 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUBDtxO1BebV46f796q/JxnJyA9SeB8WTW+i40oU++M3Ig+91w2LSdw8LXOcpdSN5l/RSVfdA==@linaro.org X-Google-Smtp-Source: AGHT+IGmvZG1jzdhK/qrmIZq309qL4NFWiutHZy8jFkBLsJu6YMT/iqM3aKHu9FoY9TO/4kbp+N8 X-Received: by 2002:a05:622a:38e:b0:471:ba68:b59b with SMTP id d75a77b69052e-4761093fca0mr52194641cf.6.1741373985479; Fri, 07 Mar 2025 10:59:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1741373985; cv=none; d=google.com; s=arc-20240605; b=FZVVYlHJoCK++CVGeFltd2Lg92Hr1DER/AMNbteaMAIHP7//7ibCFH/ew3a5iklJwW /LW6XRx0K40+Wwc/zOQrpbQTV6ftEIttTknK8PasUB13ZmeM4/nw9zXmmlBztDCPZ4Z6 dCaXAEvGOQjo/y4m/xYOp6X/F9B7TVYcDEd0NJqUaykXrMGZ+MsuvFukah6EzF+2c4e0 tnnZ/aM96VgqnTguM6C2GD4k5ZOy0b7WrtruurHSasL1EbSEeaUhlba1TZFoBpCpb64i bsoUPj7EsTmKHKKbgCer7EdZ3N09C2Mb+oT5AGSFKOHw5OhTDGPiLMKvsa5UnanzwUk+ w0mQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HdNSdlVsW8pmir+q1TpDvW924tsDK1wZFdH64G2NXCE=; fh=qKKfiElUquWdkyrWxyzPwUbXApIM0f/sdIVQxneHhZM=; b=Ru8X0EV7n5kLpJhAVnmnx5BAj5icBjfk2W05GdEdD1sEG0rG2sZGFEgL6GegD0n2mY hfq9exHoIfSUxje4TLBELe5MIL7ipj6LuOW/ry4u6H8BhZCtLl1cFdevEUVYQxgPZbT1 QLrgJgvPboS2IOJEg13geL14//N4lJtjTJ9HgZCRi7BKdSbAbM8BciIqu6IGRBJZsW/X 44uotuY2I08VDM82mx8WdIJgnQqpFz/G2K6gpEw5+zwH5UlAoe5+oYEJ0UWosvNlfW9b TnprapnhysCfFdwhNqr6LLO4p/tFA0jzyFAeoBnB/tNcJf7gyoAvSYObnpUDI1MSVaRR ft2g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hCxtWCyJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-4751db4277fsi41103511cf.514.2025.03.07.10.59.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Mar 2025 10:59:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hCxtWCyJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcsZ-0007V8-BJ; Fri, 07 Mar 2025 13:57:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsS-0007SN-JK for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:57 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsQ-0007mq-H7 for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:55 -0500 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2ff797f8f1bso2548909a91.3 for ; Fri, 07 Mar 2025 10:56:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373813; x=1741978613; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HdNSdlVsW8pmir+q1TpDvW924tsDK1wZFdH64G2NXCE=; b=hCxtWCyJkDSYF/RTpfTFbkcHBgm1GJpLlAyKT5Xwmw/QKxiS943UKZJuiUX7mGkS+w j2+WOwnkSKP5d8M/Yj+Zn3imkh+jyfswmX7XANHIJnqhJpRoq9BkXu0dS1JnTIIwAzBn BKqnPEcBtLEm+XjZvUCq2VnMCkie2o4fwJlk1tKnyi0PjOo/+d6jgx7zNayrKXZkN56K i0nHUBNUj4K6gKpHHyOzY41fXZVgqJw0kFlVmb5i3IxeccyJVajoyO0Zo/I4MSUM50rm 6yeyFwBvAGmCErHzjdMSyVV+zHSEdKnt/H3K8e94CQji40QzTTSdbkE3vxaUr3VBi3wp DupQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373813; x=1741978613; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HdNSdlVsW8pmir+q1TpDvW924tsDK1wZFdH64G2NXCE=; b=gF9rCi7Lpqm349e/sa1qXxivcID///pK1xn12y1pS/WfwbknSygSEHpG1eiuJ9NZtF Bzxh3KDH965Q8YmZtDO6f8C3ESWEAKMNqe3RhD+z9hxMN/SgmuHc0JWyeiqdBRvo+ljn mq1J+z5BZ2HcbbHWDbORV2/KViw6cJGXb8grQmJUXNsTpkiEMyXrBvOatVYk4UFwtfmf cMN3ADRbviFS5geIJO3Iua3HLZAuYk8kwxo28dTQ1x5Df3kvf8fMjPHRIUuXWqIL2yLG hvhjbG40K+Cg5umsM+yRufNHiZzabqPWVoBFRv6oGffBDeRbjKU/JR4cJIJVXYRr02Ge FtuQ== X-Gm-Message-State: AOJu0Yy6DEKtATVr2WF6UUiNvYET28dfEzTx6p5q+uInNqIcBknk+6JZ o3pm8BLnX4DVlitoCG6zCtaBu3JBM5TYWb0uckMIMvqljgsQwLofiIfOO4+gKVAByn0fM731j8Q p X-Gm-Gg: ASbGncs8ivlmjW4Y3vxuoDO2A3wkg5V8G6aXS4zOA/2MEklV/zmEQa5GTKGiFFHUXD4 5NIfH6n/9Vj/5/aZuY+uI5nUbSgaU7Sp3KByc6N3FOoamCF3A3Soz7jYXQtbWQIDe7cC+UN0G1X jPrrJaHH6pvsIYFt4EFbT2U7FXW3PTiop/sVVr+7sq8fc56zyIV8zXJrA3CK8o8Z7qrYuaOulzr UEcFMfEKgR39D3HDe078GTV59tiv650fdUB5424EamB+9eOTPp54qi5oTGkfck/OwzS28ZpCtF3 b9CkuRnkGbx4gHaoYu8YDWRw2KeG+1MD0Xhr8/UOqgFFT/cg/j3VKMRTyX2+fYW1ZlTU0ofFtax U X-Received: by 2002:a17:90b:2d83:b0:2fc:3264:3666 with SMTP id 98e67ed59e1d1-2ff7cf317c3mr6389177a91.30.1741373813034; Fri, 07 Mar 2025 10:56:53 -0800 (PST) Received: from stoup.. (174-21-74-48.tukw.qwest.net. [174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 07/16] exec: Declare tlb_hit*() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:36 -0800 Message-ID: <20250307185645.970034-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-20-philmd@linaro.org> --- include/exec/cpu-all.h | 23 ----------------------- accel/tcg/cputlb.c | 23 +++++++++++++++++++++++ 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 9e6724097c..8cd6c00cf8 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -179,29 +179,6 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); -/** - * tlb_hit_page: return true if page aligned @addr is a hit against the - * TLB entry @tlb_addr - * - * @addr: virtual address to test (must be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) -{ - return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); -} - -/** - * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr - * - * @addr: virtual address to test (need not be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) -{ - return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); -} - #endif /* !CONFIG_USER_ONLY */ /* Validate correct placement of CPUArchState. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c8761683a0..fb22048876 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1201,6 +1201,29 @@ void tlb_set_page(CPUState *cpu, vaddr addr, prot, mmu_idx, size); } +/** + * tlb_hit_page: return true if page aligned @addr is a hit against the + * TLB entry @tlb_addr + * + * @addr: virtual address to test (must be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) +{ + return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); +} + +/** + * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr + * + * @addr: virtual address to test (need not be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) +{ + return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); +} + /* * Note: tlb_fill_align() can trigger a resize of the TLB. * This means that all of the caller's prior references to the TLB table