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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c01d2cdsm10044042f8f.57.2025.03.08.13.37.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 13:37:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, BALATON Zoltan Cc: =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrey Smirnov , Bernhard Beschow , Jean-Christophe Dubois , Guenter Roeck , qemu-block@nongnu.org, Bin Meng , qemu-arm@nongnu.org Subject: [PATCH v4 08/14] hw/sd/sdhci: Simplify MemoryRegionOps endianness check Date: Sat, 8 Mar 2025 22:36:34 +0100 Message-ID: <20250308213640.13138-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308213640.13138-1-philmd@linaro.org> References: <20250308213640.13138-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While little endianness is the default, ome controllers might be only implemented in big endianness. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ae485f90dfe..a2e7162e289 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1444,20 +1444,10 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) SDHCIClass *sc = SYSBUS_SDHCI_GET_CLASS(s); const char *class_name = object_get_typename(OBJECT(s)); - s->io_ops = sc->io_ops ?: &sdhci_mmio_le_ops; - switch (s->endianness) { - case DEVICE_LITTLE_ENDIAN: - /* s->io_ops is little endian by default */ - break; - case DEVICE_BIG_ENDIAN: - if (s->io_ops != &sdhci_mmio_le_ops) { - error_setg(errp, "SD controller doesn't support big endianness"); - return; - } - s->io_ops = &sdhci_mmio_be_ops; - break; - default: - error_setg(errp, "Incorrect endianness"); + s->io_ops = sc->io_ops ?: (s->endianness == DEVICE_BIG_ENDIAN ? + &sdhci_mmio_be_ops : &sdhci_mmio_le_ops); + if (s->io_ops->endianness != s->endianness) { + error_setg(errp, "Invalid endianness for SD controller"); return; }