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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c103f57sm13217968f8f.91.2025.03.09.17.07.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:07:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?utf-8?q?Danie?= =?utf-8?q?l_P=2E_Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?utf-8?q?Philippe_Mathieu-Da?= =?utf-8?q?ud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 12/14] hw/sd/sdhci: Implement Freescale eSDHC as TYPE_FSL_ESDHC Date: Mon, 10 Mar 2025 01:06:18 +0100 Message-ID: <20250310000620.70120-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Per the MPC8569E reference manual, its SDHC I/O range is 4KiB wide, mapped in big endian order, and it only accepts 32-bit aligned access. Set the default register reset values. Reported-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 44 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index b21adcab670..e8fced5eedc 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -171,6 +171,8 @@ DECLARE_CLASS_CHECKERS(SDHCIClass, PCI_SDHCI, #define TYPE_SYSBUS_SDHCI "generic-sdhci" OBJECT_DECLARE_TYPE(SDHCIState, SDHCIClass, SYSBUS_SDHCI) +#define TYPE_FSL_ESDHC "fsl-esdhc" + #define TYPE_IMX_USDHC "imx-usdhc" #define TYPE_S3C_SDHCI "s3c-sdhci" diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index f731b1a141a..47e4bd1a610 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1667,7 +1667,44 @@ static void sdhci_bus_class_init(ObjectClass *klass, void *data) sbc->set_readonly = sdhci_set_readonly; } -/* --- qdev i.MX eSDHC --- */ +/* --- Freescale eSDHC (MPC8569ERM Rev.2 from 06/2011) --- */ + +static const MemoryRegionOps fsl_esdhc_mmio_ops = { + .read = sdhci_read, + .write = sdhci_write, + .valid = { + /* + * Per the reference manual (chapter 16): + * + * All eSDHC registers must be accessed as aligned 4-byte quantities. + * Accesses to the eSDHC registers that are less than 4-bytes are not + * supported. + */ + .min_access_size = 4, + .unaligned = false + }, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void fsl_esdhc_class_init(ObjectClass *oc, void *data) +{ + SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); + + sc->iomem_size = 0x1000; + sc->io_ops = &fsl_esdhc_mmio_ops; + sc->ro.capareg = 0x01e30000; + sc->reset.sdmasysad = 8; + sc->reset.blkcnt = 8; + sc->reset.prnsts = 0xff800000; + sc->reset.hostctl1 = 0x20; /* Endian mode (address-invariant) */ + sc->reset.clkcon = 0x8000; + sc->reset.norintstsen = 0x013f; + sc->reset.errintstsen = 0x117f; + + sdhci_common_class_init(oc, data); +} + +/* --- qdev i.MX uSDHC --- */ #define USDHC_MIX_CTRL 0x48 @@ -1997,6 +2034,11 @@ static const TypeInfo sdhci_types[] = { .class_size = sizeof(SDHCIClass), .class_init = sdhci_sysbus_class_init, }, + { + .name = TYPE_FSL_ESDHC, + .parent = TYPE_SYSBUS_SDHCI, + .class_init = fsl_esdhc_class_init, + }, { .name = TYPE_IMX_USDHC, .parent = TYPE_SYSBUS_SDHCI,