Message ID | 20250314131637.371866-15-peter.maydell@linaro.org |
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State | New |
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[PULL,01/17] target/arm: Move A32_BANKED_REG_{GET, SET} macros to cpregs.h
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diff --git a/util/cacheflush.c b/util/cacheflush.c index a08906155a9..1d12899a392 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -279,9 +279,11 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) for (p = rw & -dcache_lsize; p < rw + len; p += dcache_lsize) { asm volatile("dc\tcvau, %0" : : "r" (p) : "memory"); } - asm volatile("dsb\tish" : : : "memory"); } + /* DSB unconditionally to ensure any outstanding writes are committed. */ + asm volatile("dsb\tish" : : : "memory"); + /* * If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point * of Unification is not required for instruction to data coherence.