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[92.88.170.184]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec147c9dbsm35295975e9.0.2025.04.03.16.49.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 16:49:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Markus Armbruster , Richard Henderson , Pierrick Bouvier Subject: [RFC PATCH-for-10.1 06/19] target/tricore: Replace TARGET_LONG_BITS -> target_long_bits() Date: Fri, 4 Apr 2025 01:49:01 +0200 Message-ID: <20250403234914.9154-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403234914.9154-1-philmd@linaro.org> References: <20250403234914.9154-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/tricore/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 7cd26d8eaba..ad959f3b0a1 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -24,6 +24,7 @@ #include "tcg/tcg-op.h" #include "accel/tcg/cpu-ldst.h" #include "qemu/qemu-print.h" +#include "qemu/target_info.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -5922,6 +5923,7 @@ static void decode_rr_logical_shift(DisasContext *ctx) { uint32_t op2; int r3, r2, r1; + unsigned long_bits = target_long_bits(); r3 = MASK_OP_RR_D(ctx->opcode); r2 = MASK_OP_RR_S2(ctx->opcode); @@ -5937,7 +5939,7 @@ static void decode_rr_logical_shift(DisasContext *ctx) break; case OPC2_32_RR_CLO: tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); - tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], long_bits); break; case OPC2_32_RR_CLO_H: gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); @@ -5949,7 +5951,7 @@ static void decode_rr_logical_shift(DisasContext *ctx) gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); break; case OPC2_32_RR_CLZ: - tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], long_bits); break; case OPC2_32_RR_CLZ_H: gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);