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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec16313edsm60101395e9.6.2025.04.04.15.35.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 04 Apr 2025 15:35:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Gustavo Romero , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 3/9] target/arm: Remove use of TARGET_AARCH64 in arm_cpu_initfn() Date: Sat, 5 Apr 2025 00:35:15 +0200 Message-ID: <20250404223521.38781-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250404223521.38781-1-philmd@linaro.org> References: <20250404223521.38781-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce the QOM arm_cpu_is_64bit() helper, which checks whether a vCPU parent class is TYPE_AARCH64_CPU. Use it in arm_cpu_initfn() to remove a TARGET_AARCH64 definition use. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 95afa9b72f1..ef95f31f249 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1471,6 +1471,13 @@ uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) return cpu->mp_affinity; } +#ifdef CONFIG_USER_ONLY +static bool arm_cpu_is_64bit(ARMCPU *cpu) +{ + return !!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU); +} +#endif + static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -1482,16 +1489,16 @@ static void arm_cpu_initfn(Object *obj) QLIST_INIT(&cpu->el_change_hooks); #ifdef CONFIG_USER_ONLY -# ifdef TARGET_AARCH64 - /* - * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. - * These values were chosen to fit within the default signal frame. - * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, - * and our corresponding cpu property. - */ - cpu->sve_default_vq = 4; - cpu->sme_default_vq = 2; -# endif + if (arm_cpu_is_64bit(cpu)) { + /* + * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. + * These values were chosen to fit within the default signal frame. + * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, + * and our corresponding cpu property. + */ + cpu->sve_default_vq = 4; + cpu->sme_default_vq = 2; + } #else /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) {