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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec342a3dfsm57630445e9.4.2025.04.04.15.36.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 04 Apr 2025 15:36:02 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Gustavo Romero , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 8/9] linux-user/arm: Implement MTE stubs for 32-bit user emulation Date: Sat, 5 Apr 2025 00:35:20 +0200 Message-ID: <20250404223521.38781-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250404223521.38781-1-philmd@linaro.org> References: <20250404223521.38781-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We want to build MTE code once, but on linux-user it calls arm_set_mte_tcf0() which is only defined for Aarch64. Expose the declaration on 32-bit ARM by renaming aarch64/mte_user_helper.h -> arm/mte_user_helper.h, then add a stub in arm/mte_user_helper.c. Signed-off-by: Philippe Mathieu-Daudé --- linux-user/aarch64/mte_user_helper.h | 27 +--------------------- linux-user/arm/mte_user_helper.h | 34 ++++++++++++++++++++++++++++ linux-user/arm/mte_user_helper.c | 13 +++++++++++ linux-user/arm/meson.build | 2 ++ 4 files changed, 50 insertions(+), 26 deletions(-) create mode 100644 linux-user/arm/mte_user_helper.h create mode 100644 linux-user/arm/mte_user_helper.c diff --git a/linux-user/aarch64/mte_user_helper.h b/linux-user/aarch64/mte_user_helper.h index 0c53abda222..63f63abff62 100644 --- a/linux-user/aarch64/mte_user_helper.h +++ b/linux-user/aarch64/mte_user_helper.h @@ -6,29 +6,4 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ -#ifndef AARCH64_MTE_USER_HELPER_H -#define AARCH64_MTE USER_HELPER_H - -#include "user/abitypes.h" - -#ifndef PR_MTE_TCF_SHIFT -# define PR_MTE_TCF_SHIFT 1 -# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) -# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) -# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) -# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) -# define PR_MTE_TAG_SHIFT 3 -# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) -#endif - -/** - * arm_set_mte_tcf0 - Set TCF0 field in SCTLR_EL1 register - * @env: The CPU environment - * @value: The value to be set for the Tag Check Fault in EL0 field. - * - * Only SYNC and ASYNC modes can be selected. If ASYMM mode is given, the SYNC - * mode is selected instead. So, there is no way to set the ASYMM mode. - */ -void arm_set_mte_tcf0(CPUArchState *env, abi_long value); - -#endif /* AARCH64_MTE_USER_HELPER_H */ +#include "../arm/mte_user_helper.h" diff --git a/linux-user/arm/mte_user_helper.h b/linux-user/arm/mte_user_helper.h new file mode 100644 index 00000000000..0c53abda222 --- /dev/null +++ b/linux-user/arm/mte_user_helper.h @@ -0,0 +1,34 @@ +/* + * ARM MemTag convenience functions. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef AARCH64_MTE_USER_HELPER_H +#define AARCH64_MTE USER_HELPER_H + +#include "user/abitypes.h" + +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) +#endif + +/** + * arm_set_mte_tcf0 - Set TCF0 field in SCTLR_EL1 register + * @env: The CPU environment + * @value: The value to be set for the Tag Check Fault in EL0 field. + * + * Only SYNC and ASYNC modes can be selected. If ASYMM mode is given, the SYNC + * mode is selected instead. So, there is no way to set the ASYMM mode. + */ +void arm_set_mte_tcf0(CPUArchState *env, abi_long value); + +#endif /* AARCH64_MTE_USER_HELPER_H */ diff --git a/linux-user/arm/mte_user_helper.c b/linux-user/arm/mte_user_helper.c new file mode 100644 index 00000000000..6fd19dc1073 --- /dev/null +++ b/linux-user/arm/mte_user_helper.c @@ -0,0 +1,13 @@ +/* + * ARM ARM MemTag user emulation stubs. + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "mte_user_helper.h" + +void arm_set_mte_tcf0(CPUArchState *env, abi_long value) +{ + g_assert_not_reached(); +} diff --git a/linux-user/arm/meson.build b/linux-user/arm/meson.build index 348ffb810d7..95e8c078e29 100644 --- a/linux-user/arm/meson.build +++ b/linux-user/arm/meson.build @@ -24,3 +24,5 @@ vdso_le_inc = gen_vdso.process('vdso-le.so', linux_user_ss.add(when: 'TARGET_ARM', if_true: [ vdso_be8_inc, vdso_be32_inc, vdso_le_inc ]) + +linux_user_ss.add(when: 'TARGET_ARM', if_true: [files('mte_user_helper.c')])